Add synth_ice40_dsp tests

architecture/synth_ice40_dsp/assert_area.py

+#!/usr/bin/python3
+
+import glob
+import re
+import os
+
+re_mux = re.compile(r'mul_(\d+)(s?)_(\d+)(s?)_A?B?P?_A?B?P?\.v')
+
+for fn in glob.glob('*.v'):
+    m = re_mux.match(fn)
+    if not m: continue
+
+    A,B = map(int, m.group(1,3))
+    X = (A+15) // 16
+    Y = (B+15) // 16
+    count_MAC = X * Y
+    count_CARRY = 0
+    if X > 1 and Y > 1:
+        count_CARRY = X + Y - 16
+
+    bn,_ = os.path.splitext(fn)
+
+    with open(fn, 'a') as f:
+        print('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd {0}; select t:SB_MAC16 -assert-count {1}; select t:SB_CARRY -assert-count {2}; select t:SB_LUT -assert-count {2}; select t:* t:SB_MAC16 t:SB_CARRY t:SB_LUT %D %D %D -assert-none";
+endmodule
+`endif
+'''.format(os.path.splitext(fn)[0], count_MAC, count_CARRY), file=f)

architecture/synth_ice40_dsp/generate_mul.py

+#!/usr/bin/env python3
+
+from common_mul import gen_mul
+
+ARange = ['16','16s','24','24s','32','32s', '48', '48s']
+BRange = ['16','16s','24','24s','32','32s']
+
+if __name__ == "__main__":
+    gen_mul(ARange, BRange)

architecture/synth_ice40_dsp/run-test.sh

+#!/bin/bash
+set -e
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+#wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/generate.py -O generate_mul.py -o /dev/null
+cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
+PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
+python3 ../assert_area.py
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
+    -p 'design -copy-to __test __test; \
+        synth_ice40 -dsp; \
+        design -copy-from __test *; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/ice40/cells_sim.v"