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yosys-tests
Unverified Commit d27d0d87 by Miodrag Milanović Committed by GitHub
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Merge pull request #19 from SergeyDegtyar/master 

Add new tests to simple and misc groups
parents 8d41c2f9 d42079e7
Showing with 2943 additions and 6 deletions
misc/Makefile
......@@ -171,5 +171,13 @@ $(eval $(call template,log, log log_stdout log_stderr log_nolog log_n))
#tee
$(eval $(call template,tee, tee))
#test_autotb
$(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n test_autotb_seed))
#abc
$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
.PHONY: all clean
misc/abc/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/abc_dff/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
misc/abc_mux/top.v 0 → 100644
module top (
input [7:0] S,
input [255:0] D,
output M256
);
assign M256 = D[S];
endmodule
misc/scripts/abc_D.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc -D 2
misc/scripts/abc_S.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -S 2
misc/scripts/abc_g_aig.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -g aig
misc/scripts/abc_g_cmos2.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -g cmos2
misc/scripts/abc_g_simple.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc -g simple
misc/scripts/abc_mux16.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -mux16
misc/scripts/abc_mux4.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -mux4
misc/scripts/abc_mux8.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -mux8
misc/scripts/test_autotb.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_autotb
misc/scripts/test_autotb_file.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_autotb t.v
misc/scripts/test_autotb_n.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_autotb -n 200 t.v
misc/scripts/test_autotb_seed.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_autotb -seed a
misc/test_autotb/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
simple/Makefile
......@@ -75,13 +75,14 @@ $(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcove
$(eval $(call template,aigmap,aigmap aigmap_nand))
#memory_memx, memory_nordff(75-101 not covered), memory_unpack(91-108 not covered)
$(eval $(call template,memory,memory_memx memory_nordff memory_unpack))
$(eval $(call template,memory,memory_memx memory_nordff memory_unpack memory_nomap memory_nordff_opt memory_memx_opt memory_bram_opt memory_share))
#uniquify
$(eval $(call template,uniquify,uniquify))
#hierarchy (44% increased to 61,3%)
$(eval $(call template,hierarchy,hierarchy hierarchy_top hierarchy_check hierarchy_simcheck hierarchy_purge_lib hierarchy_libdir hierarchy_keep_positionals hierarchy_keep_portwidths hierarchy_nokeep_asserts hierarchy_auto_top hierarchy_generate))
$(eval $(call template,hierarchy_huge,hierarchy_huge))
#attrmap
$(eval $(call template,attrmap,attrmap attrmap_modattr))
......@@ -156,5 +157,38 @@ $(eval $(call template,share_macc, share_force_macc share_aggressive_macc share_
#make: *** [Makefile:152: share_fsm/work_share_force/.stamp] Error 1
#$(eval $(call template,share_fsm, share share_force share_aggressive share_fast share_limit))
#opt_expr
$(eval $(call template,opt_expr, opt_expr))
#ice40_dsp
$(eval $(call template,ice40_dsp_mult, ice40_dsp))
$(eval $(call template,ice40_dsp_mult_b_larger, ice40_dsp))
$(eval $(call template,ice40_dsp_mult_a_larger, ice40_dsp))
$(eval $(call template,ice40_dsp_mult_out_larger, ice40_dsp))
$(eval $(call template,ice40_dsp_mult_acc, ice40_dsp))
$(eval $(call template,ice40_dsp_mult_signed, ice40_dsp))
#opt_lut
$(eval $(call template,opt_lut, opt_lut opt_lut_limit opt_lut_dlogic opt_lut_limit_0))
$(eval $(call template,opt_lut_ice40, opt_lut opt_lut_limit opt_lut_dlogic opt_lut_limit_0))
#wreduce -memx
$(eval $(call template,wreduce_memx, wreduce_memx))
#opt_merge -share_all
$(eval $(call template,opt_merge_share_all, opt_merge_share_all))
$(eval $(call template,opt_merge_reduce, opt_merge_share_all))
#opt
$(eval $(call template,opt, opt opt_mux_bool opt_clkinv opt_share_all opt_purge opt_keepdc))
#proc_arst
$(eval $(call template,proc_arst, proc_arst proc_arst_global_rst))
$(eval $(call template,proc_arst_reduce, proc_arst proc_arst_global_rst proc_arst_global_rst_a))
#submod
$(eval $(call template, submod, submod submod_top submod_copy submod_name submod_no_proc submod_no_hier))
$(eval $(call template, submod_mem, submod submod_top submod_copy submod_name submod_no_proc submod_no_hier submod_mem))
.PHONY: all clean
simple/common.v
......@@ -7,7 +7,7 @@ module assert_dff(input clk, input test, input pat);
$stop;
end
end
endmodule
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
......@@ -33,6 +33,18 @@ module assert_Z(input clk, input A);
end
endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
......
simple/hierarchy_huge/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/hierarchy_huge/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module adff
( inout d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
parameter S=0;
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
parameter Z=1'bZ;
initial begin
q = Z;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( d, clk, pre, clr, q );
parameter s=2;
parameter l=1;
input [s-1:l] d;
input clk, pre, clr;
output reg [s-1:l] q;
initial begin
q = 2'b11;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 2'b00;
`else
q <= d;
`endif
else if ( !pre )
q <= 2'b11;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
wire a1,b11;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr #(4) u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d ({a,a1} ),
.q ({b1,b11} )
);
defparam u_ndffnsnr.l = 0;
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/hierarchy_huge/yosys_rocket/AsyncResetReg.v 0 → 100644
// See LICENSE.SiFive for license details.
/** This black-boxes an Async Reset
* Reg.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/reset.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
module AsyncResetReg (d, q, en, clk, rst);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which reset
// is not actually asserted cleanly at time 0,
// and we want to make sure to properly model
// that, yet Chisel codebase is absolutely intolerant
// of Xs.
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
q = _RAND[0];
`endif // RANDOMIZE
if (rst) begin
q = RESET_VALUE;
end
end
`endif
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= RESET_VALUE;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg
simple/hierarchy_huge/yosys_rocket/EICG_wrapper.v 0 → 100644
/* verilator lint_off UNOPTFLAT */
module EICG_wrapper(
output out,
input en,
input in
);
reg en_latched /*verilator clock_enable*/;
always @(en or in) begin
if (!in) begin
en_latched = en;
end
end
assign out = en_latched && in;
endmodule
simple/hierarchy_huge/yosys_rocket/SimDTM.v 0 → 100644
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
/*
import "DPI-C" function int debug_tick
(
output bit debug_req_valid,
input bit debug_req_ready,
output int debug_req_bits_addr,
output int debug_req_bits_op,
output int debug_req_bits_data,
input bit debug_resp_valid,
output bit debug_resp_ready,
input int debug_resp_bits_resp,
input int debug_resp_bits_data
);
*/
module SimDTM(
input clk,
input reset,
output debug_req_valid,
input debug_req_ready,
output [ 6:0] debug_req_bits_addr,
output [ 1:0] debug_req_bits_op,
output [31:0] debug_req_bits_data,
input debug_resp_valid,
output debug_resp_ready,
input [ 1:0] debug_resp_bits_resp,
input [31:0] debug_resp_bits_data,
output [31:0] exit
);
assign debug_req_valid = 0;
assign debug_req_bits_addr = 0;
assign debug_req_bits_op = 0;
assign debug_req_bits_data = 0;
assign debug_resp_ready = 0;
assign exit = 0;
/*
bit r_reset;
wire #0.1 __debug_req_ready = debug_req_ready;
wire #0.1 __debug_resp_valid = debug_resp_valid;
wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
bit __debug_req_valid;
int __debug_req_bits_addr;
int __debug_req_bits_op;
int __debug_req_bits_data;
bit __debug_resp_ready;
int __exit;
assign #0.1 debug_req_valid = __debug_req_valid;
assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
assign #0.1 debug_resp_ready = __debug_resp_ready;
assign #0.1 exit = __exit;
always @(posedge clk)
begin
r_reset <= reset;
if (reset || r_reset)
begin
__debug_req_valid = 0;
__debug_resp_ready = 0;
__exit = 0;
end
else
begin
__exit = debug_tick(
__debug_req_valid,
__debug_req_ready,
__debug_req_bits_addr,
__debug_req_bits_op,
__debug_req_bits_data,
__debug_resp_valid,
__debug_resp_ready,
__debug_resp_bits_resp,
__debug_resp_bits_data
);
end
end
*/
endmodule
simple/hierarchy_huge/yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
simple/hierarchy_huge/yosys_rocket/plusarg_reader.v 0 → 100644
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(parameter FORMAT="borked=%d", DEFAULT=0) (
output [31:0] out
);
`ifdef SYNTHESIS
assign out = DEFAULT;
`else
reg [31:0] myplus;
assign out = myplus;
initial begin
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
end
`endif
endmodule
simple/ice40_dsp_mult/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] dinA;
reg [15:0] dinB;
reg carryin;
reg rst;
wire [31:0] p;
top uut_macc (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule
module uut_macc_checker(input clk, input [15:0] A, input [15:0] B, input C, input [31:0] P);
reg [31:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/ice40_dsp_mult/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [31:0] P;
input [15:0] A;
input [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg [31:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
`ifndef BUG
P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end
endmodule
module top (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input carryin,
output [31:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple/ice40_dsp_mult_a_larger/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] dinA;
reg [17:0] dinB;
reg carryin;
reg rst;
wire [47:0] p;
top uut_macc (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule
module uut_macc_checker(input clk, input [15:0] A, input [17:0] B, input C, input [47:0] P);
reg [47:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/ice40_dsp_mult_a_larger/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
`ifndef BUG
P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple/ice40_dsp_mult_acc/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] dinA;
reg [7:0] dinB;
reg carryin;
reg rst;
wire [15:0] p;
top uut_macc (.clk(clk), .dataa(dinA), .datab(dinB), .aclr(1'b0), .clken(1'b1), .sload(1'b1), .adder_out(p));
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(1'b0), .P(p));
endmodule
module uut_macc_checker(input clk, input [7:0] A, input [7:0] B, input C, input [15:0] P);
reg [15:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/ice40_dsp_mult_acc/top.v 0 → 100644
module top
(
input [7:0] dataa,
input [7:0] datab,
input clk, aclr, clken, sload,
output reg [15:0] adder_out
);
// Declare registers and wires
reg [15:0] dataa_reg, datab_reg;
reg sload_reg;
reg [15:0] old_result;
wire [15:0] multa;
// Store the results of the operations on the current data
assign multa = dataa_reg * datab_reg;
// Store the value of the accumulation (or clear it)
always @ (adder_out, sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
old_result <= adder_out;
end
// Clear or update data, as appropriate
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
simple/ice40_dsp_mult_b_larger/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [24:0] dinA;
reg [17:0] dinB;
reg carryin;
reg rst;
wire [47:0] p;
top uut_macc (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule
module uut_macc_checker(input clk, input [24:0] A, input [17:0] B, input C, input [47:0] P);
reg [47:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/ice40_dsp_mult_b_larger/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [15:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
`ifndef BUG
P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end
endmodule
module top (
input clk,
input rst,
input [15:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple/ice40_dsp_mult_out_larger/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] dinA;
reg [15:0] dinB;
reg carryin;
reg rst;
wire [47:0] p;
top uut_macc (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule
module uut_macc_checker(input clk, input [15:0] A, input [15:0] B, input C, input [47:0] P);
reg [47:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/ice40_dsp_mult_out_larger/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [15:0] A;
input [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
`ifndef BUG
P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end
endmodule
module top (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple/ice40_dsp_mult_signed/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] dinA;
reg [15:0] dinB;
reg carryin;
reg rst;
wire [31:0] p;
top uut_macc (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule
module uut_macc_checker(input clk, input [15:0] A, input [15:0] B, input C, input [31:0] P);
reg [31:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/ice40_dsp_mult_signed/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg signed [31:0] P;
input signed [15:0] A;
input signed [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg signed [31:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
`ifndef BUG
P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end
endmodule
module top (
input clk,
input rst,
input signed [15:0] a,
input signed [15:0] b,
input carryin,
output signed [31:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple/opt/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
simple/opt/top.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
input [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt[0] <= 1;
`else
gnt[0] <= 1'bZ;
`endif
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple/opt_expr/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.clr (1'b0 ),
.pre (1'b0 ),
.a (dinA ),
.b (doutB )
);
always @(negedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule
simple/opt_expr/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( negedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
`ifndef BUG
.clr (clr),
.pre (pre),
`else
.clr (1'b0),
.pre (1'b0),
`endif
.d (a ),
.q (b )
);
endmodule
simple/opt_lut/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [24:0] dinA;
reg [17:0] dinB;
reg carryin;
reg rst;
wire [47:0] p;
top uut_macc (
.p (p),
.a (dinA),
.b (dinB),
.carryin (carryin ),
.clk (clk),
.rst (rst)
);
initial begin
rst <= 0;
#5
rst <= 1;
#5
@(posedge clk);
dinA <= 38;
dinB <= 22;
carryin <= 1;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 33;
dinB <= 12;
carryin <= 0;
repeat (10) @(posedge clk);
dinA <= 0;
dinB <= 0;
carryin <= 0;
end
uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule
module uut_macc_checker(input clk, input [24:0] A, input [17:0] B, input C, input [47:0] P);
reg [47:0] p;
always @(posedge clk)
begin
#20
p <= (A * B) + C;
if (P != p)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$stop;
end
end
endmodule
simple/opt_lut/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
`ifndef BUG
P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p,
output [47:0] pw
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
MACC u_MACC_1 (
.P (pw),
.A (a),
.B (b ),
.CARRYIN (~carryin ),
.CLK (~clk),
.RST (~rst)
);
endmodule
simple/opt_lut_ice40/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [8:0] a = 0;
reg [8:0] b = 0;
wire [8:0] o1,o1p;
wire [2:0] o2,o2p;
reg [2:0] c = 0;
reg [2:0] d = 0;
wire [2:0] o3,o3p;
wire [2:0] o4,o4p;
reg s = 0;
top uut_top (
.a(a),
.b(b),
.o1(o1),
.o2(o2),
.c(c),
.d(d),
.o3(o3),
.o4(o4),
.s(s)
);
always @(posedge clk)
begin
s <= ~s;
a <= a + 12;
b <= b + 33;
c <= c + 17;
d <= d + 22;
end
assign o1p = (s ? 0 : a + b);
assign o2p = (s ? a : a - b);
assign o3p = (s ? 4'b1111 : d + c);
assign o4p = (s ? d : c - d);
uut_top_checker o1_check(.clk(clk), .A(o1), .B(o1p));
uut_top_checker o2_check(.clk(clk), .A(o2), .B(o2p));
uut_top_checker o3_check(.clk(clk), .A(o3), .B(o3p));
uut_top_checker o4_check(.clk(clk), .A(o4), .B(o4p));
endmodule
module uut_top_checker(input clk, input [2:0] A, input [2:0] B);
always @(posedge clk)
begin
//#20
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
//$stop;
end
end
endmodule
simple/opt_lut_ice40/top.v 0 → 100644
module top(
input [8:0] a,
input [8:0] b,
output [8:0] o1,
output [2:0] o2,
input [2:0] c,
input [2:0] d,
output [2:0] o3,
output [2:0] o4,
input s
);
assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);
endmodule
simple/opt_merge_reduce/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
simple/opt_merge_reduce/top.v 0 → 100644
module top
(
input x,
input [2:0] y,
input [2:0] cin,
output A,
output cout
);
wire A1,cout1;
wire [2:0] n_y;
wire [2:0] n_cin;
// initial begin
// A = 0;
// cout = 0;
// end
assign n_y[0] = ~y[0];
assign n_y[1] = y[1];
assign n_y[2] = ~y[2];
assign n_cin[0] = ~cin[0];
assign n_cin[1] = cin[1];
assign n_cin[2] = ~cin[2];
`ifndef BUG
assign A1 = n_y + &(~cin);
assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
simple/opt_merge_share_all/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] a;
wire [31:0] c;
always @(posedge clk)
begin
a = a + 3;
end
top uut (clk, a, c);
uut_checker c_test(.clk(clk), .A(c), .B(c));
endmodule
module uut_checker(input clk, input [31:0] A, input [31:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
simple/opt_merge_share_all/top.v 0 → 100644
`ifdef FORMAL
`define assume(_expr_) assume(_expr_)
`else
`define assume(_expr_)
`endif
module top(input clk, input [4:0] addr, output reg [31:0] data);
reg [31:0] mem [0:31];
always @(posedge clk)
data <= mem[addr];
reg [31:0] used_addr = 0;
reg [31:0] used_dbits = 0;
reg initstate = 1;
always @(posedge clk) begin
initstate <= 1;
if (!initstate) begin
//`assume(data != 0);
//`assume((used_dbits & data) == 0);
end
end
endmodule
simple/proc_arst/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/proc_arst/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple/proc_arst_reduce/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/proc_arst_reduce/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input [2:0] rst;
input [1:0] a;
wire rst_or;
assign rst_or = |rst;
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple/scripts/hierarchy_huge.ys 0 → 100644
read_verilog ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/SimDTM.v
proc
hierarchy -generate -check -simcheck -purge_lib -keep_positionals -keep_portwidths -nokeep_asserts -auto-top
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
simple/scripts/ice40_dsp.ys 0 → 100644
read_verilog ../top.v
proc
ice40_dsp
synth_ice40 -top top
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory.ys 0 → 100644
read_verilog ../top.v
proc
memory
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_bram_opt.ys 0 → 100644
read_verilog ../top.v
proc
memory -bram ../words.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_memx.ys
read_verilog ../top.v
proc
memory_memx
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
write_verilog synth.v
simple/scripts/memory_memx_opt.ys 0 → 100644
read_verilog ../top.v
proc
memory -memx
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_nomap.ys 0 → 100644
read_verilog ../top.v
proc
memory -nomap
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_nordff.ys
read_verilog ../top.v
proc
memory_collect
memory_nordff
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
write_verilog synth.v
simple/scripts/memory_nordff_opt.ys 0 → 100644
read_verilog ../top.v
proc
memory -nordff
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_share.ys 0 → 100644
read_verilog ../top.v
proc
memory_share
memory
memory_share
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_unpack.ys
read_verilog ../top.v
proc
memory_collect
memory_memx
memory_unpack
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
write_verilog synth.v
simple/scripts/opt.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt
synth -top top
write_verilog synth.v
simple/scripts/opt_clkinv.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -clkinv
synth -top top
write_verilog synth.v
simple/scripts/opt_expr.ys 0 → 100644
read_verilog ../top.v
synth -top top
opt_expr
proc
opt_expr
flatten
opt
opt_expr
write_verilog synth.v
simple/scripts/opt_keepdc.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -keepdc
synth -top top
write_verilog synth.v
simple/scripts/opt_lut.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_dlogic.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -dlogic $_ANDNOT_:A=I0
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_fsm.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
fsm_detect
opt_lut
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_limit.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -limit 2
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_limit_0.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -limit 0
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_macc.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
alumacc
opt_lut
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_mem.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut
memory_collect
opt_lut
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_merge_share_all.ys 0 → 100644
read_verilog -formal ../top.v
hierarchy
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge -share_all
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple/scripts/opt_mux_bool.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -mux_bool
synth -top top
write_verilog synth.v
simple/scripts/opt_purge.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -purge
synth -top top
write_verilog synth.v
simple/scripts/opt_share_all.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -share_all
synth -top top
write_verilog synth.v
simple/scripts/proc_arst.ys 0 → 100644
read_verilog ../top.v
proc_arst
synth -top top
write_verilog synth.v
simple/scripts/proc_arst_global_rst.ys 0 → 100644
read_verilog ../top.v
proc_arst -global_arst top/rst
synth -top top
write_verilog synth.v
simple/scripts/proc_arst_global_rst_a.ys 0 → 100644
read_verilog ../top.v
proc_arst -global_arst a
synth -top top
write_verilog synth.v
simple/scripts/submod.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod
synth -top top
write_verilog synth.v
simple/scripts/submod_copy.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -copy
synth -top top
write_verilog synth.v
simple/scripts/submod_mem.ys 0 → 100644
read_verilog ../top.v
memory_memx
proc
submod
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/submod_name.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -copy -name a top
synth -top top
write_verilog synth.v
simple/scripts/submod_no_hier.ys 0 → 100644
read_verilog ../top.v
proc
submod
synth -top top
write_verilog synth.v
simple/scripts/submod_no_proc.ys 0 → 100644
read_verilog ../top.v
submod
synth -top top
write_verilog synth.v
simple/scripts/submod_top.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -copy top
synth -top top
write_verilog synth.v
simple/scripts/wreduce_memx.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple/share_shr/top.v
module top (
out,
out1,
clk,
in
);
output [7:0] out;
input clk, in;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
......@@ -13,4 +16,10 @@ in
out[7] <= in;
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
simple/submod/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
simple/submod/top.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
inout [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt[0] <= 1;
`else
gnt[0] <= 1'bZ;
`endif
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple/submod_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/submod_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple/wreduce_memx/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/wreduce_memx/testbench_.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] a = 0;
wire [15:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.in_data (a ),
.do (y )
);
genvar index;
generate
for (index=0; index <= 15; index=index+1)
begin: gen_code_label
assert_X check_output(clk,y[index]);
end
endgenerate
endmodule
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