Merge pull request #73 from SergeyDegtyar/master

Fix regressions on build #177 and #179; 

architecture/Makefile

@@ -81,7 +81,7 @@ $(eval $(call template,synth_xilinx_dsp,synth_xilinx_dsp))
 endif
 
 #xilinx_ug901_synthesis_examples
-$(eval $(call template,xilinx_ug901_synthesis_examples, xilinx_ug901_asym_ram_sdp_read_wider xilinx_ug901_asym_ram_sdp_write_wider xilinx_ug901_asym_ram_tdp_read_first xilinx_ug901_asym_ram_tdp_write_first xilinx_ug901_black_box_1 xilinx_ug901_bytewrite_ram_1b xilinx_ug901_bytewrite_tdp_ram_nc xilinx_ug901_bytewrite_tdp_ram_readfirst2 xilinx_ug901_bytewrite_tdp_ram_rf xilinx_ug901_bytewrite_tdp_ram_wf xilinx_ug901_cmacc xilinx_ug901_cmult xilinx_ug901_dynamic_shift_registers_1 xilinx_ug901_dynpreaddmultadd xilinx_ug901_fsm_1 xilinx_ug901_latches xilinx_ug901_macc xilinx_ug901_mult_unsigned xilinx_ug901_presubmult xilinx_ug901_rams_dist xilinx_ug901_ram_simple_dual_one_clock xilinx_ug901_ram_simple_dual_two_clocks xilinx_ug901_rams_init_file xilinx_ug901_rams_pipeline xilinx_ug901_rams_sp_nc xilinx_ug901_rams_sp_rf xilinx_ug901_rams_sp_rf_rst xilinx_ug901_rams_sp_rom xilinx_ug901_rams_sp_rom_1 xilinx_ug901_rams_sp_wf xilinx_ug901_rams_tdp_rf_rf xilinx_ug901_registers_1 xilinx_ug901_sfir_shifter xilinx_ug901_shift_registers_0 xilinx_ug901_shift_registers_1 xilinx_ug901_squarediffmacc xilinx_ug901_top_mux xilinx_ug901_tristates_1 xilinx_ug901_tristates_2 xilinx_ug901_xilinx_ultraram_single_port_no_change xilinx_ug901_xilinx_ultraram_single_port_read_first xilinx_ug901_xilinx_ultraram_single_port_write_first))
+$(eval $(call template,xilinx_ug901_synthesis_examples, xilinx_ug901_asym_ram_sdp_read_wider xilinx_ug901_asym_ram_sdp_write_wider xilinx_ug901_asym_ram_tdp_read_first xilinx_ug901_asym_ram_tdp_write_first xilinx_ug901_black_box_1 xilinx_ug901_bytewrite_ram_1b xilinx_ug901_bytewrite_tdp_ram_nc xilinx_ug901_bytewrite_tdp_ram_readfirst2 xilinx_ug901_bytewrite_tdp_ram_rf xilinx_ug901_bytewrite_tdp_ram_wf xilinx_ug901_cmacc xilinx_ug901_cmult xilinx_ug901_dynamic_shift_registers_1 xilinx_ug901_dynpreaddmultadd xilinx_ug901_fsm_1 xilinx_ug901_latches xilinx_ug901_macc xilinx_ug901_mult_unsigned xilinx_ug901_presubmult xilinx_ug901_rams_dist xilinx_ug901_ram_simple_dual_one_clock xilinx_ug901_ram_simple_dual_two_clocks xilinx_ug901_rams_init_file xilinx_ug901_rams_pipeline xilinx_ug901_rams_sp_nc xilinx_ug901_rams_sp_rf xilinx_ug901_rams_sp_rf_rst xilinx_ug901_rams_sp_rom xilinx_ug901_rams_sp_rom_1 xilinx_ug901_rams_sp_wf xilinx_ug901_rams_tdp_rf_rf xilinx_ug901_registers_1 xilinx_ug901_sfir_shifter xilinx_ug901_shift_registers_0 xilinx_ug901_shift_registers_1 xilinx_ug901_squarediffmacc xilinx_ug901_squarediffmult xilinx_ug901_top_mux xilinx_ug901_tristates_1 xilinx_ug901_tristates_2 xilinx_ug901_xilinx_ultraram_single_port_no_change xilinx_ug901_xilinx_ultraram_single_port_read_first xilinx_ug901_xilinx_ultraram_single_port_write_first))
 
 #greenpak4
 $(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))

architecture/run.sh

@@ -100,9 +100,9 @@ else
 	elif [ "$1" = "synth_ice40_fulladder" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "ice40_wrapcarry" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v  $TECHLIBS_PREFIX/ice40/abc_model.v
 	elif [ "$1" = "ice40_wrapcarry_adders" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v  $TECHLIBS_PREFIX/ice40/abc_model.v
 	elif [ "$1" = "synth_intel" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
 	elif [ "$1" = "synth_intel_a10gx" ]; then

architecture/scripts/xilinx_ug901_cmacc.ys

@@ -9,17 +9,11 @@ cd cmacc
 #Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
 stat
 select -assert-count 1 t:BUFG
-select -assert-count 77 t:FDRE
-select -assert-count 5 t:LUT1
-select -assert-count 46 t:LUT2
-select -assert-count 25 t:LUT3
-select -assert-count 8 t:LUT4
-select -assert-count 16 t:LUT5
-select -assert-count 85 t:LUT6
-select -assert-count 54 t:MUXCY
-select -assert-count 8 t:MUXF7
-select -assert-count 2 t:MUXF8
-select -assert-count 22 t:SRL16E
-select -assert-count 62 t:XORCY
+select -assert-count 65 t:FDRE
+select -assert-count 3 t:DSP48E1
+select -assert-count 18 t:LUT2
+select -assert-count 34 t:LUT3
+select -assert-count 25 t:MUXCY
+select -assert-count 29 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:MUXCY t:XORCY %% t:* %D

architecture/scripts/xilinx_ug901_cmult.ys

@@ -15,17 +15,10 @@ design -load postopt
 cd cmult
 #Vivado synthesizes 3 DSP48E1, 68 FDRE.
 select -assert-count 1 t:BUFG
-select -assert-count 144 t:FDRE
-select -assert-count 9 t:LUT1
-select -assert-count 176 t:LUT2
-select -assert-count 36 t:LUT3
-select -assert-count 51 t:LUT4
-select -assert-count 35 t:LUT5
-select -assert-count 343 t:LUT6
-select -assert-count 111 t:MUXCY
-select -assert-count 60 t:MUXF7
-select -assert-count 21 t:MUXF8
-select -assert-count 43 t:SRL16E
-select -assert-count 119 t:XORCY
+select -assert-count 86 t:FDRE
+select -assert-count 3 t:DSP48E1
+select -assert-count 34 t:LUT2
+select -assert-count 17 t:MUXCY
+select -assert-count 19 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D

architecture/scripts/xilinx_ug901_dynpreaddmultadd.ys

@@ -16,16 +16,12 @@ cd dynpreaddmultadd
 
 #Vivado synthesizes 1 DSP48E1.
 select -assert-count 1 t:BUFG
-select -assert-count 75 t:FDRE
+select -assert-count 24 t:FDRE
+select -assert-count 1 t:DSP48E1
 select -assert-count 8 t:LUT1
-select -assert-count 131 t:LUT2
-select -assert-count 19 t:LUT3
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:LUT5
-select -assert-count 142 t:LUT6
-select -assert-count 48 t:MUXCY
-select -assert-count 50 t:MUXF7
-select -assert-count 15 t:MUXF8
-select -assert-count 52 t:XORCY
+select -assert-count 17 t:LUT2
+select -assert-count 25 t:LUT4
+select -assert-count 16 t:MUXCY
+select -assert-count 18 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT1 t:LUT2 t:LUT4 t:MUXCY t:XORCY %% t:* %D

architecture/scripts/xilinx_ug901_latches.ys

@@ -5,6 +5,5 @@ flatten
 synth_xilinx
 #Vivado synthesizes 1 BUFG, 8 LDCE.
 select -assert-count 2 t:LUT2
-select -assert-count 1 t:$_DLATCH_P_
-#ERROR: Assertion failed: selection is not empty: t:LUT2 t:$_DLATCH_P_ %% t:* %D
-#select -assert-none t:LUT2 t:$_DLATCH_P_ %% t:* %D
+select -assert-count 1 t:LDCE
+#select -assert-none t:LUT2 t:LDCE %% t:* %D

architecture/scripts/xilinx_ug901_macc.ys

@@ -9,15 +9,7 @@ cd macc
 #Vivado synthesizes 1 DSP48E1, 1 FDRE. (When SIZEIN = 12, SIZEOUT = 30)
 stat
 select -assert-count 1 t:BUFG
-select -assert-count 53 t:FDRE
-select -assert-count 63 t:LUT2
-select -assert-count 11 t:LUT3
-select -assert-count 22 t:LUT4
-select -assert-count 13 t:LUT5
-select -assert-count 129 t:LUT6
-select -assert-count 34 t:MUXCY
-select -assert-count 45 t:MUXF7
-select -assert-count 15 t:MUXF8
-select -assert-count 36 t:XORCY
+select -assert-count 1 t:FDRE
+select -assert-count 1 t:DSP48E1
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D

architecture/scripts/xilinx_ug901_mult_unsigned.ys

@@ -16,14 +16,6 @@ cd mult_unsigned
 
 #Vivado synthesizes 1 DSP48E1, 40 FDRE.
 select -assert-count 1 t:BUFG
-select -assert-count 20 t:FDRE
-select -assert-count 33 t:LUT2
-select -assert-count 1 t:LUT3
-select -assert-count 11 t:LUT4
-select -assert-count 4 t:LUT5
-select -assert-count 139 t:LUT6
-select -assert-count 19 t:MUXCY
-select -assert-count 35 t:MUXF7
-select -assert-count 20 t:SRL16E
-select -assert-count 20 t:XORCY
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:SRL16E t:XORCY %% t:* %D
+select -assert-count 40 t:FDRE
+select -assert-count 1 t:DSP48E1
+select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D

architecture/scripts/xilinx_ug901_presubmult.ys

@@ -9,15 +9,9 @@ cd presubmult
 #Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
 stat
 select -assert-count 1 t:BUFG
-select -assert-count 51 t:FDRE
-select -assert-count 75 t:LUT2
-select -assert-count 10 t:LUT3
-select -assert-count 24 t:LUT4
-select -assert-count 15 t:LUT5
-select -assert-count 136 t:LUT6
-select -assert-count 24 t:MUXCY
-select -assert-count 46 t:MUXF7
-select -assert-count 14 t:MUXF8
-select -assert-count 26 t:XORCY
+select -assert-count 1 t:DSP48E1
+select -assert-count 16 t:LUT2
+select -assert-count 8 t:MUXCY
+select -assert-count 9 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
+select -assert-none t:BUFG t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D

architecture/scripts/xilinx_ug901_squarediffmacc.ys

@@ -9,15 +9,10 @@ cd squarediffmacc
 #Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
 stat
 select -assert-count 1 t:BUFG
-select -assert-count 64 t:FDRE
-select -assert-count 78 t:LUT2
-select -assert-count 7 t:LUT3
-select -assert-count 11 t:LUT4
-select -assert-count 8 t:LUT5
-select -assert-count 125 t:LUT6
-select -assert-count 44 t:MUXCY
-select -assert-count 50 t:MUXF7
-select -assert-count 17 t:MUXF8
-select -assert-count 47 t:XORCY
+select -assert-count 1 t:DSP48E1
+select -assert-count 17 t:FDRE
+select -assert-count 16 t:LUT2
+select -assert-count 8 t:MUXCY
+select -assert-count 9 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
+select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D

architecture/scripts/xilinx_ug901_squarediffmult.ys

@@ -16,15 +16,10 @@ cd squarediffmult
 stat
 #Vivado synthesizes 16 FDRE, 1 DSP48E1.
 select -assert-count 1 t:BUFG
-select -assert-count 117 t:FDRE
-select -assert-count 223 t:LUT2
-select -assert-count 50 t:LUT3
-select -assert-count 38 t:LUT4
-select -assert-count 56 t:LUT5
-select -assert-count 372 t:LUT6
-select -assert-count 49 t:MUXCY
-select -assert-count 99 t:MUXF7
-select -assert-count 26 t:MUXF8
-select -assert-count 51 t:XORCY
+select -assert-count 1 t:DSP48E1
+select -assert-count 32 t:FDRE
+select -assert-count 65 t:LUT2
+select -assert-count 16 t:MUXCY
+select -assert-count 17 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
+select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D

architecture/xilinx_ug901_synthesis_examples/macc.v

@@ -2,10 +2,7 @@
 // File: macc.v
 //
 module macc  # (
-				//Default parameters were changed because of slow test
-               // parameter SIZEIN = 16, SIZEOUT = 40
-               // parameter SIZEIN = 12, SIZEOUT = 30
-                parameter SIZEIN = 8, SIZEOUT = 20
+		parameter SIZEIN = 16, SIZEOUT = 40
                )
                (
                 input clk, ce, sload,