Add new tests for closed issues

regression/Makefile

@@ -404,6 +404,73 @@ $(eval $(call template,issue_00993,issue_00993))
 #issue_00997
 $(eval $(call template,issue_00997,issue_00997))
 
+#issue_01002
+$(eval $(call template,issue_01002,issue_01002))
+
+#issue_01009
+$(eval $(call template,issue_01009,issue_01009))
+
+#issue_01016
+$(eval $(call template,issue_01016,issue_01016))
+
+#issue_01022
+$(eval $(call template,issue_01022,issue_01022))
+
+#issue_01023
+$(eval $(call template,issue_01023,issue_01023))
+
+#issue_01033
+$(eval $(call template,issue_01033,issue_01033))
+
+#issue_01034
+$(eval $(call template,issue_01034,issue_01034))
+
+#issue_01040
+$(eval $(call template,issue_01040,issue_01040))
+
+#issue_01047
+$(eval $(call template,issue_01047,issue_01047))
+
+#issue_01063
+$(eval $(call template,issue_01063,issue_01063))
+
+#issue_01065
+$(eval $(call template,issue_01065,issue_01065))
+
+#issue_01070
+$(eval $(call template,issue_01070,issue_01070))
+
+#issue_01084
+$(eval $(call template,issue_01084,issue_01084))
+
+#issue_01091
+$(eval $(call template,issue_01091,issue_01091))
+
+#issue_01093
+$(eval $(call template,issue_01093,issue_01093))
+
+#issue_01115
+$(eval $(call template,issue_01115,issue_01115))
+
+#issue_01118
+$(eval $(call template,issue_01118,issue_01118))
+
+#issue_01128
+$(eval $(call template,issue_01128,issue_01128))
+
+#issue_01131
+$(eval $(call template,issue_01131,issue_01131))
+
+#issue_01132
+$(eval $(call template,issue_01132,issue_01132))
+
+#issue_01135
+$(eval $(call template,issue_01135,issue_01135))
+
+#issue_01144
+$(eval $(call template,issue_01144,issue_01144))
+
+
 
 
 .PHONY: all clean

regression/issue_01002/top.v

+module onehot(i_in, o_out);
+	parameter	LG = 7;
+	localparam	WID = (1<<LG);
+	//
+	input	wire	[WID-1:0]	i_in;
+	output	reg	[LG-1:0]	o_out;
+
+	//
+	integer	N;
+
+	always @(*)
+	begin
+		o_out = 0;
+		for(N=0; N<WID; N=N+1)
+		begin
+			if (i_in[N])
+				o_out = o_out | N[LG-1:0];
+		end
+	end
+endmodule

regression/issue_01009/top.v

+(* hello *)
+module ABC(i, o);
+  input wire i;
+  output wire o;
+
+  (* p_hello *)
+  parameter p = 0;
+  assign o = i;
+endmodule

regression/issue_01016/top.v

+module mux_x(clk, in, en, out);
+   input clk, in, en;
+   output out;
+
+   assign out = en ? in : 1'bx;
+
+endmodule // latchx

regression/issue_01022/top.v

+module test(
+  output logic [31:0] b
+);
+
+  assign b = '1;
+
+endmodule

regression/issue_01023/top.v

+module mux_case_5_1(i, s, o);
+  input [4:0] i;
+  output o;
+  input [2:0] s;
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd1),
+    .B_SIGNED(32'd0),
+    .B_WIDTH(32'sd0),
+    .Y_WIDTH(32'd1)
+  ) _34_ (
+    .A(i[4]),
+    .B(),
+    .Y(o)
+  );
+endmodule

regression/issue_01033/top.v

+module dram(input [3:0] i, output [4:0] o);
+`ifdef UNPACKED
+reg val [0:0];
+`else
+reg [0:0] val;
+`endif
+initial val[0] = 1'h1;
+assign o = i + val[0];
+endmodule

regression/issue_01034/top.v

+module dram(input [3:0] i, output [4:0] o);
+`ifdef UNPACKED
+reg val [0:0];
+`else
+reg [0:0] val;
+`endif
+initial val[0] = 1'h1;
+assign o = i + val[0];
+endmodule

regression/issue_01040/top.v

+module dut_sub(input clk, input [32:2] a, output [32:2] a_l);
+
+always @(posedge clk) a_l <= a;
+
+endmodule // dut_sub
+
+
+module dut(input clk, input[32:2] a, output [32:2] a_l);
+
+dut_sub sub(.clk(clk), .a(a), .a_l(a_l));
+
+endmodule // dut

regression/issue_01047/top.v

+module top (y, w);
+   output y;
+   input [2:0] w;
+   assign y = 1'b1 >> (w * (3'b110));
+endmodule

regression/issue_01063/top.v

+module top
+(
+input x,
+input y,
+input cin,
+
+output reg A,
+output cout
+);
+parameter X = 1;
+wire o;
+
+always @(posedge cin)
+A <= o;
+
+assign cout = cin? y : x;
+
+middle u_mid1 (.x(x),.o(o),.y(1'b0));
+middle u_mid2 (.x(x),.o(o),.y(1'b1));
+middle u_mid3 (.x(x),.o(o),.y(1'bX));
+middle u_mid4 (.x(x),.o(o),.y(1'bX));
+
+endmodule
+
+module middle
+(
+input x,
+input y,
+output o
+);
+
+urtl u_urtl (.x(x),.o(o),.y(y));
+endmodule
+
+module urtl
+(
+input x,
+input y,
+output o
+);
+
+assign o = x + y;
+endmodule

regression/issue_01065/top.v

+module top(input clk);
+wire ce = 1'b1;
+reg q = 1'b0;
+always @(posedge clk)
+    if (ce) q <= 1'b0;
+
+(* keep *)
+unknown_module u(.i(q));
+endmodule

regression/issue_01070/top.v

+module top(input clk, d, output reg q);
+wire ce = 1'b1;
+always @(negedge clk)
+    if (ce) q <= d;
+endmodule

regression/issue_01084/top.v

+module top;
+initial
+   if (0) $error("ASDF");
+endmodule

regression/issue_01091/top.v

+module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      o <= i[0*W+:W];
+     else
+      o <= i[1*W+:W];
+    else
+     if (s[1] == 1'b0)
+      o <= i[2*W+:W];
+end
+endmodule

regression/issue_01093/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+//assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

regression/issue_01115/top.v

+module top(input clk, output [32:0] o);
+assign o = 'bx;
+endmodule

regression/issue_01118/top.v

+module top(output [3:0] o);
+generate
+    genvar i;
+    for (i = 3; i >= 0; i = i-1) begin
+        assign o[i] = 1'b0;
+    end
+endgenerate
+endmodule

regression/issue_01128/top.v

+module test (
+    input i,
+    output o
+);
+    wire w1;
+    wire w2;
+
+    assign w1 = ~i;
+    assign w2 = w1;
+    assign o = ~w2;
+endmodule

regression/issue_01131/top.v

+module minimal;
+reg [7:0] q;
+initial begin
+q <= '81;
+end
+endmodule

regression/issue_01132/top.v

+module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      o <= i[0*W+:W];
+     else
+      o <= i[1*W+:W];
+    else
+     if (s[1] == 1'b0)
+      o <= i[2*W+:W];
+end
+endmodule

regression/issue_01135/top.v

+module top(input [7:0] i, output o);
+always @*
+case (i[6:3])
+    4: o <= i[0];
+    3: o <= i[2];
+    7: o <= i[3];
+    default: o <= 1'b0;
+endcase
+endmodule

regression/issue_01144/top.v

+module top(input clk, d, output q);
+specify
+  // Fails:
+  (posedge clk => (q +: d)) = (3,1);
+  (/*posedge*/ clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+  (/*posedge*/ clk *> (q +: d)) = (3,1);
+
+  // Works:
+  (/*posedge*/ clk => q) = (3,1);
+  (/*posedge*/ clk *> q) = (3,1);
+endspecify
+endmodule

regression/run.sh

@@ -22,7 +22,11 @@ if [ "$1" = "issue_00089" ] ||\
    [ "$1" = "issue_00603" ] ||\
    [ "$1" = "issue_00635" ] ||\
    [ "$1" = "issue_00763" ] ||\
-   [ "$1" = "issue_00814" ]; then
+   [ "$1" = "issue_00814" ] ||\
+   [ "$1" = "issue_01063" ] ||\
+   [ "$1" = "issue_01093" ] ||\
+   [ "$1" = "issue_01131" ] ||\
+   [ "$1" = "issue_01144" ]; then
 
 	expected_string="syntax error"
     #Change checked string for check other errors
@@ -38,6 +42,12 @@ if [ "$1" = "issue_00089" ] ||\
 		expected_string="Invalid nesting"
 	elif [ "$1" = "issue_00814" ]; then
 		expected_string="is implicitly declared"
+	elif [ "$1" = "issue_01063" ]; then
+		expected_string="Gate cell u_mid8 not found in module top."
+	elif [ "$1" = "issue_01093" ]; then
+		expected_string="ERROR: Design has no top module, use the 'hierarchy' command to specify one."
+	elif [ "$1" = "issue_01131" ]; then
+		expected_string="ERROR: Value conversion failed"
 	fi
 
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
@@ -94,7 +104,25 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_00982" ] ||\
 	 [ "$1" = "issue_00987" ] ||\
 	 [ "$1" = "issue_00993" ] ||\
-	 [ "$1" = "issue_00997" ]; then
+	 [ "$1" = "issue_00997" ] ||\
+	 [ "$1" = "issue_01002" ] ||\
+	 [ "$1" = "issue_01009" ] ||\
+	 [ "$1" = "issue_01016" ] ||\
+	 [ "$1" = "issue_01022" ] ||\
+	 [ "$1" = "issue_01023" ] ||\
+	 [ "$1" = "issue_01033" ] ||\
+	 [ "$1" = "issue_01034" ] ||\
+	 [ "$1" = "issue_01040" ] ||\
+	 [ "$1" = "issue_01047" ] ||\
+	 [ "$1" = "issue_01065" ] ||\
+	 [ "$1" = "issue_01070" ] ||\
+	 [ "$1" = "issue_01084" ] ||\
+	 [ "$1" = "issue_01091" ] ||\
+	 [ "$1" = "issue_01115" ] ||\
+	 [ "$1" = "issue_01118" ] ||\
+	 [ "$1" = "issue_01128" ] ||\
+	 [ "$1" = "issue_01132" ] ||\
+	 [ "$1" = "issue_01135" ]; then
 
 	expected_string=""
 	expected="1"
@@ -182,6 +210,45 @@ elif [ "$1" = "issue_00502" ] ||\
 		expected_string="_DFF_P_                        1"
 	elif [ "$1" = "issue_00997" ]; then
 		expected_string="h0"
+	elif [ "$1" = "issue_01002" ]; then
+		expected_string="Estimated number of LCs:         95"
+	elif [ "$1" = "issue_01009" ]; then
+		expected_string="attribute \\\p_hello"
+	elif [ "$1" = "issue_01016" ]; then
+		expected_string="cell \$mux \$ternary\$../top.v:5"
+	elif [ "$1" = "issue_01022" ]; then
+		expected_string="connect \\\b 32'11111111111111111111111111111111"
+	elif [ "$1" = "issue_01023" ]; then
+		expected_string="Continuing TECHMAP pass"
+	elif [ "$1" = "issue_01033" ]; then
+		expected_string="RAM64X1D         "
+		expected="0"
+	elif [ "$1" = "issue_01034" ]; then
+		expected_string="FDRE         "
+		expected="0"
+	elif [ "$1" = "issue_01040" ]; then
+		expected_string=".subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\]"
+	elif [ "$1" = "issue_01047" ]; then
+		expected_string="assign y = ~(w\[0\] | w\[1\]);"
+	elif [ "$1" = "issue_01065" ]; then
+		expected_string="Driver-driver conflict for"
+		expected="0"
+	elif [ "$1" = "issue_01070" ]; then
+		expected_string="cell \$_DFF_N_"
+	elif [ "$1" = "issue_01084" ]; then
+		expected_string="Successfully finished Verilog frontend"
+	elif [ "$1" = "issue_01091" ]; then
+		expected_string="\$_MUX4_                         1"
+	elif [ "$1" = "issue_01115" ]; then
+		expected_string="connect \\\o 33'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
+	elif [ "$1" = "issue_01118" ]; then
+		expected_string="connect \\\o \[0\] 1'0"
+	elif [ "$1" = "issue_01128" ]; then
+		expected_string="\$_BUF_                          1"
+	elif [ "$1" = "issue_01132" ]; then
+		expected_string="\$_MUX4_                         1"
+	elif [ "$1" = "issue_01135" ]; then
+		expected_string="\$pmux                           1"
 	fi
 
 	yosys -ql yosys.log ../../scripts/$2.ys;

regression/scripts/issue_01002.ys

+read -sv ../top.v
+hierarchy -top onehot -chparam LG 7
+tee -a result.log synth_xilinx
+

regression/scripts/issue_01009.ys

+read_verilog ../top.v
+tee -a result.log dump
+

regression/scripts/issue_01016.ys

+read_verilog -sv ../top.v
+proc
+wreduce -keepdc
+tee -a result.log dump
+

regression/scripts/issue_01022.ys

+read_verilog -sv ../top.v
+tee -a result.log dump
+

regression/scripts/issue_01023.ys

+read_verilog -icells ../top.v
+tee -a result.log techmap
+

regression/scripts/issue_01033.ys

+read_verilog ../top.v
+tee -a result.log synth_xilinx
+

regression/scripts/issue_01034.ys

+read_verilog ../top.v
+tee -a result.log synth_xilinx -nodram
+

regression/scripts/issue_01040.ys

+read_verilog ../top.v
+synth
+write_blif result.log

regression/scripts/issue_01047.ys

+read -formal ../top.v
+synth
+write_verilog -noattr result.log

regression/scripts/issue_01063.ys

+read -formal ../top.v
+proc
+fmcombine top u_mid1 u_mid8

regression/scripts/issue_01065.ys

+read_verilog ../top.v
+proc
+tee -o result.log opt -fast

regression/scripts/issue_01070.ys

+read_verilog ../top.v
+proc
+dff2dffe
+simplemap
+opt
+opt_rmdff
+stat
+tee -o result.log dump

regression/scripts/issue_01084.ys

+tee -o result.log read_verilog ../top.v

regression/scripts/issue_01091.ys

+read_verilog ../top.v
+proc
+opt
+techmap
+muxcover -nopartial
+tee -o result.log stat

regression/scripts/issue_01093.ys

+read_verilog ../top.v
+proc
+tee -o result.log sim

regression/scripts/issue_01115.ys

+read_verilog ../top.v
+proc
+tee -o result.log dump

regression/scripts/issue_01118.ys

+read_verilog ../top.v
+proc
+tee -o result.log dump

regression/scripts/issue_01128.ys

+read_verilog ../top.v
+insbuf
+# select just the $_BUF_ from w1 to w2 as @buf
+select -set buf w:w1 %coe1 w:w1 %d
+# set the keep attribute for the $_BUF_ from w1 to w2
+setattr -set keep 1 @buf
+opt_clean
+tee -o result.log stat

regression/scripts/issue_01131.ys

+tee -o result.log read_verilog ../top.v

regression/scripts/issue_01132.ys

+read_verilog ../top.v
+proc; opt; wreduce; simplemap; muxcover -mux4=150
+tee -o result.log stat

regression/scripts/issue_01135.ys

+read_verilog ../top.v
+proc; pmux2shiftx -norange; opt -full
+tee -o result.log stat

regression/scripts/issue_01144.ys

+read_verilog ../top.v
+tee -o result.log stat