Review 'misc' test group (select_cd - write_file)

misc_reviewed/select_cd/select_cd.ys

+read_verilog ../top.v
+proc
+cd

misc_reviewed/select_cd/select_cd_invalid_number_of_args_fail.pat

+ERROR: Invalid number of arguments.

misc_reviewed/select_cd/select_cd_invalid_number_of_args_fail.ys

+read_verilog ../top.v
+proc
+cd sdf dfsf

misc_reviewed/select_cd/select_cd_module.ys

+read_verilog ../top.v
+proc
+cd middle
+cd top

misc_reviewed/select_cd/select_cd_no_such_module_fail.pat

+ERROR: No such module `tt/tt' found!

misc_reviewed/select_cd/select_cd_no_such_module_fail.ys

+read_verilog ../top.v
+proc
+cd tt/tt

misc_reviewed/select_cd/select_cd_up.ys

+read_verilog ../top.v
+proc
+cd middle
+cd ..

misc_reviewed/select_cd/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/select_cd/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [5:0] addr_a, addr_b,
+	input we_a, we_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		else
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		else
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/select_ls/select_ls.ys

+read_verilog ../top.v
+proc
+select -add top
+tee -o result.out ls

misc_reviewed/select_ls/select_ls_top.ys

+read_verilog ../top.v
+proc
+tee -o result.out ls top

misc_reviewed/select_ls/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/setattr/setattr.ys

+read_verilog ../top.v
+proc
+setattr

misc_reviewed/setattr/setattr_cant_decode_value_fail.pat

+ERROR: Can't decode value

misc_reviewed/setattr/setattr_cant_decode_value_fail.ys

+read_verilog ../top.v
+proc
+setattr -set a af*&

misc_reviewed/setattr/setattr_mem.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_mem.ys

+read_verilog ../top_mem.v
+proc
+setattr -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_mod.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_mod.ys

+read_verilog ../top.v
+proc
+setattr -mod -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_set.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_set.ys

+read_verilog ../top.v
+proc
+setattr -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_set_proc.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_set_proc.ys

+read_verilog ../top.v
+setattr -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_top.ys

+read_verilog ../top.v
+proc
+setattr top

misc_reviewed/setattr/setattr_unset.ys

+read_verilog ../top.v
+proc
+setattr -set u 1 top
+setattr -unset u top
+tee -o result.out dump

misc_reviewed/setattr/setattr_unset_n.pat

+attribute \\u 1

misc_reviewed/setattr/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/setattr/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [5:0] addr_a, addr_b,
+	input we_a, we_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		else
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		else
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/setparam/setparam.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam

misc_reviewed/setparam/setparam_set.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam -set WIDTH 1 top

misc_reviewed/setparam/setparam_top.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam top

misc_reviewed/setparam/setparam_type.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam -type $mux -set WIDTH 1 top

misc_reviewed/setparam/setparam_unset.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam -set WIDTH 1 top
+tee -o result.log setparam -unset WIDT top

misc_reviewed/setparam/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter WIDTH = 1;
+ wire o;
+
+assign cout =  cin ? y : x;
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/setundef/setundef_anyconst.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -anyconst

misc_reviewed/setundef/setundef_anyseq.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -anyseq

misc_reviewed/setundef/setundef_expose.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -zero -expose -undriven

misc_reviewed/setundef/setundef_expose_no_val.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -expose -undriven

misc_reviewed/setundef/setundef_expose_without_undriven_fail.pat

+ERROR: Option -expose must be used with option -undriven.

misc_reviewed/setundef/setundef_expose_without_undriven_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -expose

misc_reviewed/setundef/setundef_init.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -zero -init

misc_reviewed/setundef/setundef_init_with_anyconst_fail.pat

+ERROR: The options -init and -anyseq / -anyconst are exclusive.

misc_reviewed/setundef/setundef_init_with_anyconst_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -init -anyconst

misc_reviewed/setundef/setundef_init_with_anyseq_fail.pat

+ERROR: The options -init and -anyseq / -anyconst are exclusive.

misc_reviewed/setundef/setundef_init_with_anyseq_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -init -anyseq

misc_reviewed/setundef/setundef_one.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -one

misc_reviewed/setundef/setundef_one_of_options_fail.pat

+ERROR: One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.

misc_reviewed/setundef/setundef_one_of_options_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef

misc_reviewed/setundef/setundef_params.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -params -expose -undriven

misc_reviewed/setundef/setundef_random.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -random 256

misc_reviewed/setundef/setundef_undef.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -undef

misc_reviewed/setundef/setundef_undriven.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -zero -undriven

misc_reviewed/setundef/setundef_undriven_with_process_fail.pat

+ERROR: The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.

misc_reviewed/setundef/setundef_undriven_with_process_fail.ys

+read_verilog ../top.v
+tee -o result.log setundef -undriven -zero

misc_reviewed/setundef/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+//assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/show/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

misc_reviewed/show/show.ys

+read_verilog ../top.v
+proc
+tee -o result.log show -viewer dummy.sh top

misc_reviewed/show/show_cant_open_dot_file_fail.pat

+ERROR: Can't open dot file `tt/tt.dot' for writing.

misc_reviewed/show/show_cant_open_dot_file_fail.ys

+read_verilog ../top.v
+tee -o result.log show -format dot -prefix tt/tt

misc_reviewed/show/show_cant_open_lib_file_fail.pat

+ERROR: Can't open lib file `l.lib'.

misc_reviewed/show/show_cant_open_lib_file_fail.ys

+read_verilog ../top.v
+tee -o result.log show -lib l.lib top

misc_reviewed/show/show_color.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -color red $add top

misc_reviewed/show/show_colorattr.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colorattr attr top

misc_reviewed/show/show_colors.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colors red green blue top

misc_reviewed/show/show_enum.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -enum top

misc_reviewed/show/show_format.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -format dot top

misc_reviewed/show/show_label.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -label adder $add top

misc_reviewed/show/show_lib.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -lib ../top.v top

misc_reviewed/show/show_long.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -long top

misc_reviewed/show/show_nothing_there_to_show_fail.pat

+ERROR: Nothing there to show.

misc_reviewed/show/show_nothing_there_to_show_fail.ys

+tee -o result.log show dot.dot top

misc_reviewed/show/show_notitle.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -notitle top

misc_reviewed/show/show_only_one_module_fail.pat

+ERROR: For formats different than 'ps' or 'dot' only one module must be selected.

misc_reviewed/show/show_only_one_module_fail.ys

+read_verilog ../top.v
+tee -o result.log show -format svg

misc_reviewed/show/show_pause.disable

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -pause top

misc_reviewed/show/show_pause.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -pause top

misc_reviewed/show/show_prefix.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log show -viewer dummy.sh -prefix pr top

misc_reviewed/show/show_signed.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -signed top

misc_reviewed/show/show_stretch.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -stretch top

misc_reviewed/show/show_viewer.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh top

misc_reviewed/show/show_width.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -width top

misc_reviewed/show/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/show/top_err_1.v

+module top
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/sim/sim.ys

+read_verilog -sv ../top.v
+proc
+sim top

misc_reviewed/sim/sim_a.ys

+read_verilog -sv ../top.v
+proc
+sim -a top

misc_reviewed/sim/sim_a_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -a top

misc_reviewed/sim/sim_asserts.pat

+Warning: Unsupported evaluable cell type:

misc_reviewed/sim/sim_asserts.ys

+read_verilog -sv ../top_asserts.v
+proc
+tee -o result.out sim top

misc_reviewed/sim/sim_clock.ys

+read_verilog -sv ../top.v
+proc
+sim -clock x top

misc_reviewed/sim/sim_clock_mem.ys

+read_verilog ../top_mem.v
+proc
+sim -clock clk top

misc_reviewed/sim/sim_clockn.ys

+read_verilog ../top_mem.v
+proc
+sim -clockn clk top

misc_reviewed/sim/sim_d.ys

+read_verilog -sv ../top.v
+proc
+sim -d top

misc_reviewed/sim/sim_d_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -d top

misc_reviewed/sim/sim_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim top

misc_reviewed/sim/sim_n.ys

+read_verilog -sv ../top.v
+proc
+sim -n 5 top

misc_reviewed/sim/sim_n_mem.ys

+read_verilog -sv ../top.v
+proc
+sim -n 5 top

misc_reviewed/sim/sim_reset.ys

+read_verilog ../top_mem.v
+proc
+sim -reset we_b top

misc_reviewed/sim/sim_resetn.ys

+read_verilog ../top_mem.v
+proc
+sim -resetn we_a top

misc_reviewed/sim/sim_rstlen.ys

+read_verilog -sv ../top.v
+proc
+sim -rstlen 2 top

misc_reviewed/sim/sim_rstlen_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -rstlen 2 top