Review 'misc' test group (help - select)

misc_reviewed/help/help.ys

+tee -q -o result.log help

misc_reviewed/help/help_all.ys

+tee -q -o result.log help -all

misc_reviewed/help/help_cells.ys

+tee -q -o result.log help -cells

misc_reviewed/help/help_celltype.pat

+    $dff (CLK, D, Q)
+
+No help message for this cell type found.
+
+Run 'help $dff+' to display the Verilog model for this cell type.

misc_reviewed/help/help_celltype.ys

+tee -q -o result.out help $dff

misc_reviewed/help/help_celltype_plus.pat

+module \\$dff (CLK, D, Q);
+
+    parameter WIDTH = 0;
+    parameter CLK_POLARITY = 1'b1;
+
+    input CLK;
+    input \[WIDTH-1:0\] D;
+    output reg \[WIDTH-1:0\] Q;
+    wire pos_clk = CLK == CLK_POLARITY;
+
+    always @(posedge pos_clk) begin
+        Q <= D;
+    end
+
+endmodule

misc_reviewed/help/help_celltype_plus.ys

+tee -q -o result.out help $dff+

misc_reviewed/help/help_command.pat

+read_verilog \[options\] \[filename\]

misc_reviewed/help/help_command.ys

+tee -q -o result.out help read_verilog

misc_reviewed/help/help_no_such_command.pat

+No such command or cell type: u

misc_reviewed/help/help_no_such_command.ys

+tee -q -o result.out help u

misc_reviewed/hilomap/hilomap.ys

+read_verilog ../top.v
+proc
+hilomap
+select -assert-count 1 t:$dffsr
+select -assert-count 4 t:$mux
+select -assert-count 2 t:$not
+select -assert-count 2 t:dffsr
+select -assert-none t:$dffsr t:$mux t:$not t:dffsr %% t:* %D

misc_reviewed/hilomap/hilomap_hicell.ys

+read_verilog ../top.v
+proc
+hilomap -hicell VCC V
+select -assert-count 4 t:VCC
+select -assert-count 0 t:GND

misc_reviewed/hilomap/hilomap_hicell_locell_singleton.ys

+read_verilog ../top.v
+proc
+hilomap -locell GND G -hicell VCC V -singleton
+
+select assert-count 1 t:VCC
+select assert-count 1 t:GND

misc_reviewed/hilomap/hilomap_hicell_singleton.ys

+read_verilog ../top.v
+proc
+hilomap -hicell VCC V -singleton
+
+select -assert-count 2 t:VCC
+select -assert-count 0 t:GND

misc_reviewed/hilomap/hilomap_locell.ys

+read_verilog ../top.v
+proc
+hilomap -locell GND G
+select -assert-count 0 t:VCC
+select -assert-count 6 t:GND

misc_reviewed/hilomap/hilomap_locell_singleton.ys

+read_verilog ../top.v
+proc
+hilomap -locell GND G -singleton
+select -assert-count 0 t:VCC
+select -assert-count 2 t:GND

misc_reviewed/hilomap/hilomap_singleton.ys

+read_verilog ../top.v
+proc
+hilomap -singleton

misc_reviewed/hilomap/top.v

+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( pre )
+			q <= 1'b1;
+		else if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input a,
+output b,b2
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (1'b0),
+        .pre (1'b1),
+        .d (a ),
+        .q (b )
+    );
+
+dffsr u2_dffsr (
+        .clk (clk ),
+        .clr (1'b0),
+        .pre (1'b1),
+        .d (a ),
+        .q (b2 )
+    );
+
+endmodule

misc_reviewed/history/history.ys

+read_verilog ../top.v
+proc
+synth
+synth_xilinx
+tee -o result.out  history

misc_reviewed/history/top.v

+(* black_box *) module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/insbuf/insbuf.ys

+read_verilog ../top.v
+synth
+insbuf
+select -assert-count 1 t:$_BUF_

misc_reviewed/insbuf/insbuf_cell.ys

+read_verilog ../top.v
+synth
+insbuf -buf $_NOT_ A Y
+select -assert-count 1 t:$_NOT_

misc_reviewed/insbuf/insbuf_unknown_arg.ys

+read_verilog ../top.v
+synth
+insbuf buf

misc_reviewed/insbuf/insbuf_wide.ys

+read_verilog ../top_wide.v
+synth
+insbuf
+select -assert-count 16 t:$_BUF_

misc_reviewed/insbuf/top.v

+module top    (
+out,
+i,
+clk,
+o,
+in
+);
+    output [7:0] out;
+    input clk, in;
+    reg [7:0] out;
+    input i;
+    output o;
+
+    always @(posedge clk)
+	begin
+		out    <= out << 1;
+		out[0] <= in;
+	end
+
+endmodule

misc_reviewed/insbuf/top_wide.v

+module top    (
+out,
+in
+);
+    output [7:0] out;
+    input [7:0] in;
+
+    wire [7:0] o;
+
+	assign o  = in;
+
+	assign out = o;
+
+endmodule

misc_reviewed/log/log.ys

+tee -o result.log log "OK"

misc_reviewed/log/log_n.ys

+tee -o result.log log -n "OK"

misc_reviewed/log/log_nolog.ys

+tee -o result.log log -nolog "OK"

misc_reviewed/log/log_stderr.ys

+tee -o result.log log -stderr "OK"

misc_reviewed/log/log_stdout.ys

+tee -o result.log log -stdout "OK"

misc_reviewed/ltp/ltp.pat

+Longest topological path in top (length=3):
+    0: \\x
+    1: $add$../top.v:13$2_Y (via $add$../top.v:13$2)
+    2: \\A (via $procdff$4)
+    3: $add$../top.v:15$3_Y (via $add$../top.v:15$3)

misc_reviewed/ltp/ltp.ys

+read_verilog ../top.v
+proc
+tee -o result.out ltp

misc_reviewed/ltp/ltp_loop.pat

+Warning: Detected loop at $and$../top_logic_loop.v:13$1_Y in top
+
+Longest topological path in top (length=3):
+    0: \\x
+    1: $and$../top_logic_loop.v:13$1_Y (via $and$../top_logic_loop.v:13$1)
+    2: $and$../top_logic_loop.v:14$2_Y (via $and$../top_logic_loop.v:14$2)
+    3: $not$../top_logic_loop.v:15$3_Y (via $not$../top_logic_loop.v:15$3)

misc_reviewed/ltp/ltp_loop.ys

+read_verilog ../top_logic_loop.v
+proc
+tee -o result.out ltp

misc_reviewed/ltp/ltp_noff.pat

+Longest topological path in top (length=1):
+    0: \\x
+    1: $add$../top.v:13$2_Y (via $add$../top.v:13$2)
+   ff: \\A (via $procdff$4)

misc_reviewed/ltp/ltp_noff.ys

+read_verilog ../top.v
+proc
+tee -o result.out ltp -noff

misc_reviewed/ltp/ltp_noproc.pat

+Warning: Ignoring module top because it contains processes (run 'proc' command first).

misc_reviewed/ltp/ltp_noproc.ys

+read_verilog ../top.v
+tee -o result.out ltp

misc_reviewed/ltp/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= y + x;
+
+assign cout =  cin + A;
+
+endmodule

misc_reviewed/ltp/top_logic_loop.v

+module top
+(
+ input x,
+ input y,
+ input z,
+
+ output A,
+ output B
+ );
+
+ wire A1,B1,A2,B2;
+
+ assign A1 = x & A2;
+ assign A2 = A1 & y;
+ assign A = ~A2;
+
+endmodule

misc_reviewed/miter/miter_assert.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter -assert -make_outputs top
+tee -o result.log miter -assert -make_outputs middle

misc_reviewed/miter/miter_assert_assert.ys

+read_verilog -sv ../top_assert.v
+proc
+tee -o result.log miter -assert -make_outputs top miter
+tee -o result.log miter -assert -make_outputs middle

misc_reviewed/miter/miter_assert_flatten.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter -assert -flatten top
+tee -o result.log miter -assert -flatten middle

misc_reviewed/miter/miter_cant_find_gate_module_fail.pat

+ERROR: Can't find gate module \\gate!

misc_reviewed/miter/miter_cant_find_gate_module_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter -equiv top gate top

misc_reviewed/miter/miter_cant_find_gold_module_fail.pat

+ERROR: Can't find gold module \\gold!

misc_reviewed/miter/miter_cant_find_gold_module_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter -equiv gold gate top

misc_reviewed/miter/miter_cant_find_module_fail.pat

+ERROR: Can't find module \\t!

misc_reviewed/miter/miter_cant_find_module_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter -assert t

misc_reviewed/miter/miter_equiv.ys

+read_verilog ../top_equiv.v
+hierarchy -top dut
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter

misc_reviewed/miter/miter_equiv_ignore_gold_x.ys

+read_verilog ../top_equiv.v
+hierarchy -top dut
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
+memory
+opt -full
+
+miter -equiv -flatten -ignore_gold_x -make_assert -make_outputs gold gate miter

misc_reviewed/miter/miter_equiv_outcmp.ys

+read_verilog ../top_equiv.v
+hierarchy -top dut
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
+memory
+opt -full
+
+miter -equiv -flatten -make_outcmp -make_assert -make_outputs gold gate miter

misc_reviewed/miter/miter_missing_mode_param_fail.pat

+ERROR: Missing mode parameter!

misc_reviewed/miter/miter_missing_mode_param_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter

misc_reviewed/miter/miter_no_match_in_gate_fail.pat

+ERROR: No matching port in gate module was found for \\y!

misc_reviewed/miter/miter_no_match_in_gate_fail.ys

+read_verilog -sv ../top_err_1.v
+proc
+tee -o result.log miter -equiv middle u_rtl top1

misc_reviewed/miter/miter_no_match_in_gold_fail.pat

+ERROR: No matching port in gold module was found for \\y!

misc_reviewed/miter/miter_no_match_in_gold_fail.ys

+read_verilog -sv ../top_err_1.v
+proc
+tee -o result.log miter -equiv u_rtl middle top1

misc_reviewed/miter/miter_there_is_already_a_module_fail.pat

+ERROR: There is already a module \\top!

misc_reviewed/miter/miter_there_is_already_a_module_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log miter -equiv top middle top

misc_reviewed/miter/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+//assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/miter/top_assert.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/miter/top_equiv.v

+module dut(
+	input fast_clk, slow_clk,
+	input [3:0] waddr, raddr,
+	input [3:0] wdata,
+	input wen,
+	output [3:0] rdata
+);
+
+	reg [3:0] mem[0:15];
+	reg [3:0] raddr_reg;
+
+	always @(posedge fast_clk) begin
+		if (wen)
+			mem[waddr] <= wdata;
+	end
+
+	always @(posedge slow_clk)
+		raddr_reg <= raddr;
+
+	assign rdata = mem[raddr_reg];
+endmodule

misc_reviewed/miter/top_err_1.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+//assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+//	input y,
+	output o
+);
+
+assign o = x;
+endmodule

misc_reviewed/mutate/mutate_all.ys

+read_verilog ../top.v
+mutate -list 512 -o mutate.yss
+script mutate.yss
+select -assert-count 2 t:$add
+select -assert-count 9 t:$not
+select -assert-count 3 t:$xnor
+select -assert-count 1 t:$xor

misc_reviewed/mutate/mutate_cnot0.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+select -assert-count 1 t:$xnor
+
+
+

misc_reviewed/mutate/mutate_cnot1.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src top.v:12
+
+select -assert-count 1 t:$xor
+
+
+

misc_reviewed/mutate/mutate_const0.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+stat
+
+

misc_reviewed/mutate/mutate_const1.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+stat
+

misc_reviewed/mutate/mutate_error_fail.pat

+ERROR: Invalid mode:

misc_reviewed/mutate/mutate_error_fail.ys

+read_verilog ../top.v
+tee -o result.log mutate -cell $add$../top.v:12$1 -port \Y -portbit 0 -ctrlbit 0 -module top
+

misc_reviewed/mutate/mutate_inv.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+select -assert-count 1 t:$not

misc_reviewed/mutate/mutate_list.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32
+

misc_reviewed/mutate/mutate_list_cfg.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -cfg weight_cover 1
+
+

misc_reviewed/mutate/mutate_list_ctrl.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -ctrl A 1 1
+

misc_reviewed/mutate/mutate_list_none.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -none
+

misc_reviewed/mutate/mutate_list_o.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -o o.txt
+

misc_reviewed/mutate/mutate_list_s.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -s s.txt
+help mutate
+

misc_reviewed/mutate/mutate_list_seed.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -seed 5
+

misc_reviewed/mutate/mutate_mem.ys

+read_verilog ../top_mem.v
+mutate -list 512 -o mutate.yss
+script mutate.yss
+
+

misc_reviewed/mutate/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+
+assign {cout,A} =  cin + y + x;
+
+endmodule
+

misc_reviewed/mutate/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/muxpack/muxpack.ys

+read_verilog ../top.v
+proc
+select -assert-count 13 t:$mux
+select -assert-count 1 t:$pmux
+select -assert-count 28 t:$eq
+muxpack
+select -assert-count 1 t:$mux
+select -assert-count 3 t:$pmux
+select -assert-count 28 t:$eq

misc_reviewed/muxpack/muxpack_reduce.ys

+read_verilog ../top_reduce.v
+proc
+muxpack
+select -assert-count 1  t:$pmux
+select -assert-count 16 t:$eq
+select -assert-count 8  t:$reduce_or

misc_reviewed/muxpack/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+    if (S == 0) Y <= D[0];
+    else if (S == 1) Y <= D[1];
+    else if (S == 2) Y <= D[2];
+    else if (S == 3) Y <= D[3];
+    else Y <= 1'bx;
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+    if (S == 0) Y <= D[0];
+    else if (S == 1) Y <= D[1];
+    else if (S == 2) Y <= D[2];
+    else if (S == 3) Y <= D[3];
+    else if (S == 4) Y <= D[4];
+    else if (S == 5) Y <= D[5];
+    else if (S == 6) Y <= D[6];
+    else if (S == 7) Y <= D[7];
+    else Y <= 1'bx;
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+reg Y;
+wire[3:0] S;
+wire[15:0] D;
+
+always @*
+     begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+            4 : Y = D[4];
+            5 : Y = D[5];
+            6 : Y = D[6];
+            7 : Y = D[7];
+            8 : Y = D[8];
+            9 : Y = D[9];
+            10 : Y = D[10];
+            11 : Y = D[11];
+            12 : Y = D[12];
+            13 : Y = D[13];
+            14 : Y = D[14];
+            15 : Y = D[15];
+            default: Y = 1'bx;
+        endcase
+     end
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

misc_reviewed/muxpack/top_reduce.v

+module mux (D, S, Y);
+ 	input  [7:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+reg Y;
+wire[3:0] S;
+wire[7:0] D;
+
+always @*
+     begin
+        case( S )
+            0,1 : Y = D[0];
+            2,3 : Y = D[1];
+            4,5 : Y = D[2];
+            6,7 : Y = D[3];
+            8,9 : Y = D[4];
+            10,11 : Y = D[5];
+            12,13 : Y = D[6];
+            14,15 : Y = D[7];
+            default: Y = 1'bx;
+        endcase
+     end
+
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+    if (S != 0) Y <= D[0];
+    else if (S != 1) Y <= D[1];
+    else if (S != 2) Y <= D[2];
+    else if (S != 3) Y <= D[3];
+    else Y <= 1'bx;
+
+endmodule
+

misc_reviewed/onehot/onehot.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -onehot ignore
+
+onehot
+tee -o result.out 

misc_reviewed/onehot/onehot_v.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -onehot ignore
+onehot -v
+

misc_reviewed/onehot/onehot_vv.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_1.ys

+read_verilog ../top_1.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_2.ys

+read_verilog ../top_2.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_3.ys

+read_verilog ../top_3.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_4.ys

+read_verilog ../top_4.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_5.ys

+read_verilog ../top_5.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_6.ys

+read_verilog ../top_6.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/onehot_vv_fsm.ys

+read_verilog ../top_fsm.v
+proc
+pmux2shiftx -onehot ignore
+onehot -vv
+

misc_reviewed/onehot/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule