Review 'misc' test group (select_cd - write_file)

misc_reviewed/select_cd/select_cd.ys

+read_verilog ../top.v
+proc
+cd

misc_reviewed/select_cd/select_cd_invalid_number_of_args_fail.pat

+ERROR: Invalid number of arguments.

misc_reviewed/select_cd/select_cd_invalid_number_of_args_fail.ys

+read_verilog ../top.v
+proc
+cd sdf dfsf

misc_reviewed/select_cd/select_cd_module.ys

+read_verilog ../top.v
+proc
+cd middle
+cd top

misc_reviewed/select_cd/select_cd_no_such_module_fail.pat

+ERROR: No such module `tt/tt' found!

misc_reviewed/select_cd/select_cd_no_such_module_fail.ys

+read_verilog ../top.v
+proc
+cd tt/tt

misc_reviewed/select_cd/select_cd_up.ys

+read_verilog ../top.v
+proc
+cd middle
+cd ..

misc_reviewed/select_cd/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/select_cd/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [5:0] addr_a, addr_b,
+	input we_a, we_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		else
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		else
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/select_ls/select_ls.ys

+read_verilog ../top.v
+proc
+select -add top
+tee -o result.out ls

misc_reviewed/select_ls/select_ls_top.ys

+read_verilog ../top.v
+proc
+tee -o result.out ls top

misc_reviewed/select_ls/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/setattr/setattr.ys

+read_verilog ../top.v
+proc
+setattr

misc_reviewed/setattr/setattr_cant_decode_value_fail.pat

+ERROR: Can't decode value

misc_reviewed/setattr/setattr_cant_decode_value_fail.ys

+read_verilog ../top.v
+proc
+setattr -set a af*&

misc_reviewed/setattr/setattr_mem.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_mem.ys

+read_verilog ../top_mem.v
+proc
+setattr -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_mod.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_mod.ys

+read_verilog ../top.v
+proc
+setattr -mod -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_set.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_set.ys

+read_verilog ../top.v
+proc
+setattr -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_set_proc.pat

+attribute \\u 1

misc_reviewed/setattr/setattr_set_proc.ys

+read_verilog ../top.v
+setattr -set u 1 top
+tee -o result.out dump

misc_reviewed/setattr/setattr_top.ys

+read_verilog ../top.v
+proc
+setattr top

misc_reviewed/setattr/setattr_unset.ys

+read_verilog ../top.v
+proc
+setattr -set u 1 top
+setattr -unset u top
+tee -o result.out dump

misc_reviewed/setattr/setattr_unset_n.pat

+attribute \\u 1

misc_reviewed/setattr/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/setattr/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [5:0] addr_a, addr_b,
+	input we_a, we_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		else
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		else
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/setparam/setparam.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam

misc_reviewed/setparam/setparam_set.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam -set WIDTH 1 top

misc_reviewed/setparam/setparam_top.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam top

misc_reviewed/setparam/setparam_type.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam -type $mux -set WIDTH 1 top

misc_reviewed/setparam/setparam_unset.ys

+read_verilog ../top.v
+proc
+tee -o result.log setparam -set WIDTH 1 top
+tee -o result.log setparam -unset WIDT top

misc_reviewed/setparam/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter WIDTH = 1;
+ wire o;
+
+assign cout =  cin ? y : x;
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/setundef/setundef_anyconst.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -anyconst

misc_reviewed/setundef/setundef_anyseq.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -anyseq

misc_reviewed/setundef/setundef_expose.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -zero -expose -undriven

misc_reviewed/setundef/setundef_expose_no_val.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -expose -undriven

misc_reviewed/setundef/setundef_expose_without_undriven_fail.pat

+ERROR: Option -expose must be used with option -undriven.

misc_reviewed/setundef/setundef_expose_without_undriven_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -expose

misc_reviewed/setundef/setundef_init.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -zero -init

misc_reviewed/setundef/setundef_init_with_anyconst_fail.pat

+ERROR: The options -init and -anyseq / -anyconst are exclusive.

misc_reviewed/setundef/setundef_init_with_anyconst_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -init -anyconst

misc_reviewed/setundef/setundef_init_with_anyseq_fail.pat

+ERROR: The options -init and -anyseq / -anyconst are exclusive.

misc_reviewed/setundef/setundef_init_with_anyseq_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -init -anyseq

misc_reviewed/setundef/setundef_one.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -one

misc_reviewed/setundef/setundef_one_of_options_fail.pat

+ERROR: One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.

misc_reviewed/setundef/setundef_one_of_options_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef

misc_reviewed/setundef/setundef_params.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -params -expose -undriven

misc_reviewed/setundef/setundef_random.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -random 256

misc_reviewed/setundef/setundef_undef.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -undef

misc_reviewed/setundef/setundef_undriven.ys

+read_verilog ../top.v
+proc
+tee -o result.log setundef -zero -undriven

misc_reviewed/setundef/setundef_undriven_with_process_fail.pat

+ERROR: The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.

misc_reviewed/setundef/setundef_undriven_with_process_fail.ys

+read_verilog ../top.v
+tee -o result.log setundef -undriven -zero

misc_reviewed/setundef/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+//assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/show/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

misc_reviewed/show/show.ys

+read_verilog ../top.v
+proc
+tee -o result.log show -viewer dummy.sh top

misc_reviewed/show/show_cant_open_dot_file_fail.pat

+ERROR: Can't open dot file `tt/tt.dot' for writing.

misc_reviewed/show/show_cant_open_dot_file_fail.ys

+read_verilog ../top.v
+tee -o result.log show -format dot -prefix tt/tt

misc_reviewed/show/show_cant_open_lib_file_fail.pat

+ERROR: Can't open lib file `l.lib'.

misc_reviewed/show/show_cant_open_lib_file_fail.ys

+read_verilog ../top.v
+tee -o result.log show -lib l.lib top

misc_reviewed/show/show_color.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -color red $add top

misc_reviewed/show/show_colorattr.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colorattr attr top

misc_reviewed/show/show_colors.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -colors red green blue top

misc_reviewed/show/show_enum.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -enum top

misc_reviewed/show/show_format.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -format dot top

misc_reviewed/show/show_label.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -label adder $add top

misc_reviewed/show/show_lib.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -lib ../top.v top

misc_reviewed/show/show_long.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -long top

misc_reviewed/show/show_nothing_there_to_show_fail.pat

+ERROR: Nothing there to show.

misc_reviewed/show/show_nothing_there_to_show_fail.ys

+tee -o result.log show dot.dot top

misc_reviewed/show/show_notitle.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -notitle top

misc_reviewed/show/show_only_one_module_fail.pat

+ERROR: For formats different than 'ps' or 'dot' only one module must be selected.

misc_reviewed/show/show_only_one_module_fail.ys

+read_verilog ../top.v
+tee -o result.log show -format svg

misc_reviewed/show/show_pause.disable

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -pause top

misc_reviewed/show/show_pause.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -pause top

misc_reviewed/show/show_prefix.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log show -viewer dummy.sh -prefix pr top

misc_reviewed/show/show_signed.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -signed top

misc_reviewed/show/show_stretch.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -stretch top

misc_reviewed/show/show_viewer.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh top

misc_reviewed/show/show_width.ys

+read_verilog ../top.v
+tee -o result.log show -viewer dummy.sh -width top

misc_reviewed/show/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/show/top_err_1.v

+module top
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/sim/sim.ys

+read_verilog -sv ../top.v
+proc
+sim top

misc_reviewed/sim/sim_a.ys

+read_verilog -sv ../top.v
+proc
+sim -a top

misc_reviewed/sim/sim_a_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -a top

misc_reviewed/sim/sim_asserts.pat

+Warning: Unsupported evaluable cell type:

misc_reviewed/sim/sim_asserts.ys

+read_verilog -sv ../top_asserts.v
+proc
+tee -o result.out sim top

misc_reviewed/sim/sim_clock.ys

+read_verilog -sv ../top.v
+proc
+sim -clock x top

misc_reviewed/sim/sim_clock_mem.ys

+read_verilog ../top_mem.v
+proc
+sim -clock clk top

misc_reviewed/sim/sim_clockn.ys

+read_verilog ../top_mem.v
+proc
+sim -clockn clk top

misc_reviewed/sim/sim_d.ys

+read_verilog -sv ../top.v
+proc
+sim -d top

misc_reviewed/sim/sim_d_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -d top

misc_reviewed/sim/sim_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim top

misc_reviewed/sim/sim_n.ys

+read_verilog -sv ../top.v
+proc
+sim -n 5 top

misc_reviewed/sim/sim_n_mem.ys

+read_verilog -sv ../top.v
+proc
+sim -n 5 top

misc_reviewed/sim/sim_reset.ys

+read_verilog ../top_mem.v
+proc
+sim -reset we_b top

misc_reviewed/sim/sim_resetn.ys

+read_verilog ../top_mem.v
+proc
+sim -resetn we_a top

misc_reviewed/sim/sim_rstlen.ys

+read_verilog -sv ../top.v
+proc
+sim -rstlen 2 top

misc_reviewed/sim/sim_rstlen_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -rstlen 2 top

misc_reviewed/sim/sim_vcd.ys

+read_verilog -sv ../top.v
+proc
+sim -vcd vcd.vcd top

misc_reviewed/sim/sim_vcd_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -vcd vcd.vcd top

misc_reviewed/sim/sim_w.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -w top

misc_reviewed/sim/sim_w_mem.ys

+read_verilog -sv ../top_mem.v
+proc
+sim -w top

misc_reviewed/sim/sim_zinit.ys

+read_verilog -sv ../top.v
+proc
+sim -zinit top

misc_reviewed/sim/sim_zinit_mem.ys

+read_verilog ../top_mem.v
+memory_collect
+proc
+sim -zinit top

misc_reviewed/sim/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+
+always @(posedge cin)
+	A <= o;
+
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/sim/top_asserts.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

misc_reviewed/sim/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [5:0] addr_a, addr_b,
+	input we_a, we_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		else
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		else
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/splice/splice.ys

+read_verilog ../top.v
+splice
+proc
+splice
+synth
+splice
+dump

misc_reviewed/splice/splice_no_outputs.ys

+read_verilog ../top.v
+synth
+splice -no_outputs
+dump

misc_reviewed/splice/splice_no_port.ys

+read_verilog ../top.v
+synth
+splice -no_port q_b
+dump

misc_reviewed/splice/splice_port.ys

+read_verilog ../top.v
+synth
+splice -port WR_EN
+dump

misc_reviewed/splice/splice_port_and_no_port_fail.pat

+ERROR: The options -port and -no_port are exclusive!

misc_reviewed/splice/splice_port_and_no_port_fail.ys

+read_verilog ../top.v
+synth
+splice -port WR_EN -no_port q_b
+dump

misc_reviewed/splice/splice_sel_any_bit.ys

+read_verilog ../top.v
+synth
+splice -sel_any_bit
+dump

misc_reviewed/splice/splice_sel_by_cell.ys

+read_verilog ../top.v
+synth
+splice -sel_by_cell
+dump

misc_reviewed/splice/splice_sel_by_cell_and_sel_any_bit_fail.pat

+ERROR: The options -sel_by_cell and -sel_any_bit are exclusive!

misc_reviewed/splice/splice_sel_by_cell_and_sel_any_bit_fail.ys

+read_verilog ../top.v
+synth
+splice -sel_by_cell -sel_any_bit
+dump

misc_reviewed/splice/splice_sel_by_cell_and_sel_by_wire_fail.pat

+ERROR: The options -sel_by_cell and -sel_by_wire are exclusive!

misc_reviewed/splice/splice_sel_by_cell_and_sel_by_wire_fail.ys

+read_verilog ../top.v
+synth
+splice -sel_by_cell -sel_by_wire
+dump

misc_reviewed/splice/splice_sel_by_wire.ys

+read_verilog ../top.v
+synth
+splice -sel_by_wire
+dump

misc_reviewed/splice/splice_wires.ys

+read_verilog ../top.v
+synth
+splice -wires
+dump

misc_reviewed/splice/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/splitnets/splitnets.ys

+read_verilog -sv ../top.v
+splitnets
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_dpf.ys

+read_verilog -sv ../top.v
+splitnets -driver -ports -format www
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_driver.ys

+read_verilog -sv ../top.v
+splitnets -driver
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_format.ys

+read_verilog -sv ../top.v
+splitnets -format ()
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_logic.ys

+read_verilog -sv ../top_logic.v
+splitnets
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_ports.ys

+read_verilog -sv ../top_wide_wires.v
+splitnets -ports
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_top.ys

+read_verilog -sv ../top.v
+splitnets top
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_top_reg.ys

+read_verilog -sv ../top.v
+splitnets ram
+tee -o result.log dump

misc_reviewed/splitnets/splitnets_wide.ys

+read_verilog -sv ../top_wide_wires.v
+splitnets
+tee -o result.log dump

misc_reviewed/splitnets/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/splitnets/top_logic.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

misc_reviewed/splitnets/top_wide_wires.v

+/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module top(state, key, out);
+
+    input  [127:0] state, key;
+    output [127:0] out;
+    reg    [127:0] s0, k0;
+    wire   [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
+                   k1, k2, k3, k4, k5, k6, k7, k8, k9,
+                   k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
+
+    always @ (*)
+      begin
+        s0 <= state ^ key;
+        k0 <= key;
+      end
+
+    expand_key_128
+        a1 (k0, k1, k0b, 8'h1),
+        a2 (k1, k2, k1b, 8'h2),
+        a3 (k2, k3, k2b, 8'h4),
+        a4 (k3, k4, k3b, 8'h8),
+        a5 (k4, k5, k4b, 8'h10),
+        a6 (k5, k6, k5b, 8'h20),
+        a7 (k6, k7, k6b, 8'h40),
+        a8 (k7, k8, k7b, 8'h80),
+        a9 (k8, k9, k8b, 8'h1b),
+       a10 (k9,   , k9b, 8'h36);
+
+    one_round
+        r1 (s0, k0b, s1),
+        r2 (s1, k1b, s2),
+        r3 (s2, k2b, s3),
+        r4 (s3, k3b, s4),
+        r5 (s4, k4b, s5),
+        r6 (s5, k5b, s6),
+        r7 (s6, k6b, s7),
+        r8 (s7, k7b, s8),
+        r9 (s8, k8b, s9);
+
+    final_round
+        rf (s9, k9b, out);
+endmodule
+
+module expand_key_128(in, out_1, out_2, rcon);
+
+    input      [127:0] in;
+    input      [7:0]   rcon;
+    output reg [127:0] out_1;
+    output     [127:0] out_2;
+    wire       [31:0]  k0, k1, k2, k3,
+                       v0, v1, v2, v3;
+    reg        [31:0]  k0a, k1a, k2a, k3a;
+    wire       [31:0]  k0b, k1b, k2b, k3b, k4a;
+
+    assign {k0, k1, k2, k3} = in;
+
+    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
+    assign v1 = v0 ^ k1;
+    assign v2 = v1 ^ k2;
+    assign v3 = v2 ^ k3;
+
+    always @ (*)
+        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
+
+    S4
+        S4_0 ({k3[23:0], k3[31:24]}, k4a);
+
+    assign k0b = k0a ^ k4a;
+    assign k1b = k1a ^ k4a;
+    assign k2b = k2a ^ k4a;
+    assign k3b = k3a ^ k4a;
+
+    always @ (*)
+        out_1 <= {k0b, k1b, k2b, k3b};
+
+    assign out_2 = {k0b, k1b, k2b, k3b};
+endmodule
+
+/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* one AES round for every two clock cycles */
+module one_round (state_in, key, state_out);
+    input      [127:0] state_in, key;
+    output reg [127:0] state_out;
+    wire       [31:0]  s0,  s1,  s2,  s3,
+                       z0,  z1,  z2,  z3,
+                       p00, p01, p02, p03,
+                       p10, p11, p12, p13,
+                       p20, p21, p22, p23,
+                       p30, p31, p32, p33,
+                       k0,  k1,  k2,  k3;
+
+    assign {k0, k1, k2, k3} = key;
+
+    assign {s0, s1, s2, s3} = state_in;
+
+    table_lookup
+        t0 (s0, p00, p01, p02, p03),
+        t1 (s1, p10, p11, p12, p13),
+        t2 (s2, p20, p21, p22, p23),
+        t3 (s3, p30, p31, p32, p33);
+
+    assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
+    assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
+    assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
+    assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
+
+    always @ (*)
+        state_out <= {z0, z1, z2, z3};
+endmodule
+
+/* AES final round for every two clock cycles */
+module final_round (state_in, key_in, state_out);
+    input      [127:0] state_in;
+    input      [127:0] key_in;
+    output reg [127:0] state_out;
+    wire [31:0] s0,  s1,  s2,  s3,
+                z0,  z1,  z2,  z3,
+                k0,  k1,  k2,  k3;
+    wire [7:0]  p00, p01, p02, p03,
+                p10, p11, p12, p13,
+                p20, p21, p22, p23,
+                p30, p31, p32, p33;
+
+    assign {k0, k1, k2, k3} = key_in;
+
+    assign {s0, s1, s2, s3} = state_in;
+
+    S4
+        S4_1 (s0, {p00, p01, p02, p03}),
+        S4_2 (s1, {p10, p11, p12, p13}),
+        S4_3 (s2, {p20, p21, p22, p23}),
+        S4_4 (s3, {p30, p31, p32, p33});
+
+    assign z0 = {p00, p11, p22, p33} ^ k0;
+    assign z1 = {p10, p21, p32, p03} ^ k1;
+    assign z2 = {p20, p31, p02, p13} ^ k2;
+    assign z3 = {p30, p01, p12, p23} ^ k3;
+
+    always @ (*)
+        state_out <= {z0, z1, z2, z3};
+endmodule
+
+
+/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module table_lookup (state, p0, p1, p2, p3);
+    input [31:0] state;
+    output [31:0] p0, p1, p2, p3;
+    wire [7:0] b0, b1, b2, b3;
+
+    assign {b0, b1, b2, b3} = state;
+    T
+        t0 (b0, {p0[23:0], p0[31:24]}),
+        t1 ( b1, {p1[15:0], p1[31:16]}),
+        t2 (b2, {p2[7:0],  p2[31:8]} ),
+        t3 (b3, p3);
+endmodule
+
+/* substitue four bytes in a word */
+module S4 (in, out);
+
+    input [31:0] in;
+    output [31:0] out;
+
+    S
+        S_0 (in[31:24], out[31:24]),
+        S_1 (in[23:16], out[23:16]),
+        S_2 (in[15:8],  out[15:8] ),
+        S_3 (in[7:0],   out[7:0]  );
+endmodule
+
+/* S_box, S_box, S_box*(x+1), S_box*x */
+module T (in, out);
+    input  [7:0]  in;
+    output [31:0] out;
+
+    S
+        s0 (in, out[31:24]);
+    assign out[23:16] = out[31:24];
+    xS
+        s4 (in, out[7:0]);
+    assign out[15:8] = out[23:16] ^ out[7:0];
+endmodule
+
+/* S box */
+module S (in, out);
+
+    input [7:0] in;
+    output reg [7:0] out;
+
+    always @ (*)
+    case (in)
+    8'h00: out <= 8'h63;
+    8'h01: out <= 8'h7c;
+    8'h02: out <= 8'h77;
+    8'h03: out <= 8'h7b;
+    8'h04: out <= 8'hf2;
+    8'h05: out <= 8'h6b;
+    8'h06: out <= 8'h6f;
+    8'h07: out <= 8'hc5;
+    8'h08: out <= 8'h30;
+    8'h09: out <= 8'h01;
+    8'h0a: out <= 8'h67;
+    8'h0b: out <= 8'h2b;
+    8'h0c: out <= 8'hfe;
+    8'h0d: out <= 8'hd7;
+    8'h0e: out <= 8'hab;
+    8'h0f: out <= 8'h76;
+    8'h10: out <= 8'hca;
+    8'h11: out <= 8'h82;
+    8'h12: out <= 8'hc9;
+    8'h13: out <= 8'h7d;
+    8'h14: out <= 8'hfa;
+    8'h15: out <= 8'h59;
+    8'h16: out <= 8'h47;
+    8'h17: out <= 8'hf0;
+    8'h18: out <= 8'had;
+    8'h19: out <= 8'hd4;
+    8'h1a: out <= 8'ha2;
+    8'h1b: out <= 8'haf;
+    8'h1c: out <= 8'h9c;
+    8'h1d: out <= 8'ha4;
+    8'h1e: out <= 8'h72;
+    8'h1f: out <= 8'hc0;
+    8'h20: out <= 8'hb7;
+    8'h21: out <= 8'hfd;
+    8'h22: out <= 8'h93;
+    8'h23: out <= 8'h26;
+    8'h24: out <= 8'h36;
+    8'h25: out <= 8'h3f;
+    8'h26: out <= 8'hf7;
+    8'h27: out <= 8'hcc;
+    8'h28: out <= 8'h34;
+    8'h29: out <= 8'ha5;
+    8'h2a: out <= 8'he5;
+    8'h2b: out <= 8'hf1;
+    8'h2c: out <= 8'h71;
+    8'h2d: out <= 8'hd8;
+    8'h2e: out <= 8'h31;
+    8'h2f: out <= 8'h15;
+    8'h30: out <= 8'h04;
+    8'h31: out <= 8'hc7;
+    8'h32: out <= 8'h23;
+    8'h33: out <= 8'hc3;
+    8'h34: out <= 8'h18;
+    8'h35: out <= 8'h96;
+    8'h36: out <= 8'h05;
+    8'h37: out <= 8'h9a;
+    8'h38: out <= 8'h07;
+    8'h39: out <= 8'h12;
+    8'h3a: out <= 8'h80;
+    8'h3b: out <= 8'he2;
+    8'h3c: out <= 8'heb;
+    8'h3d: out <= 8'h27;
+    8'h3e: out <= 8'hb2;
+    8'h3f: out <= 8'h75;
+    8'h40: out <= 8'h09;
+    8'h41: out <= 8'h83;
+    8'h42: out <= 8'h2c;
+    8'h43: out <= 8'h1a;
+    8'h44: out <= 8'h1b;
+    8'h45: out <= 8'h6e;
+    8'h46: out <= 8'h5a;
+    8'h47: out <= 8'ha0;
+    8'h48: out <= 8'h52;
+    8'h49: out <= 8'h3b;
+    8'h4a: out <= 8'hd6;
+    8'h4b: out <= 8'hb3;
+    8'h4c: out <= 8'h29;
+    8'h4d: out <= 8'he3;
+    8'h4e: out <= 8'h2f;
+    8'h4f: out <= 8'h84;
+    8'h50: out <= 8'h53;
+    8'h51: out <= 8'hd1;
+    8'h52: out <= 8'h00;
+    8'h53: out <= 8'hed;
+    8'h54: out <= 8'h20;
+    8'h55: out <= 8'hfc;
+    8'h56: out <= 8'hb1;
+    8'h57: out <= 8'h5b;
+    8'h58: out <= 8'h6a;
+    8'h59: out <= 8'hcb;
+    8'h5a: out <= 8'hbe;
+    8'h5b: out <= 8'h39;
+    8'h5c: out <= 8'h4a;
+    8'h5d: out <= 8'h4c;
+    8'h5e: out <= 8'h58;
+    8'h5f: out <= 8'hcf;
+    8'h60: out <= 8'hd0;
+    8'h61: out <= 8'hef;
+    8'h62: out <= 8'haa;
+    8'h63: out <= 8'hfb;
+    8'h64: out <= 8'h43;
+    8'h65: out <= 8'h4d;
+    8'h66: out <= 8'h33;
+    8'h67: out <= 8'h85;
+    8'h68: out <= 8'h45;
+    8'h69: out <= 8'hf9;
+    8'h6a: out <= 8'h02;
+    8'h6b: out <= 8'h7f;
+    8'h6c: out <= 8'h50;
+    8'h6d: out <= 8'h3c;
+    8'h6e: out <= 8'h9f;
+    8'h6f: out <= 8'ha8;
+    8'h70: out <= 8'h51;
+    8'h71: out <= 8'ha3;
+    8'h72: out <= 8'h40;
+    8'h73: out <= 8'h8f;
+    8'h74: out <= 8'h92;
+    8'h75: out <= 8'h9d;
+    8'h76: out <= 8'h38;
+    8'h77: out <= 8'hf5;
+    8'h78: out <= 8'hbc;
+    8'h79: out <= 8'hb6;
+    8'h7a: out <= 8'hda;
+    8'h7b: out <= 8'h21;
+    8'h7c: out <= 8'h10;
+    8'h7d: out <= 8'hff;
+    8'h7e: out <= 8'hf3;
+    8'h7f: out <= 8'hd2;
+    8'h80: out <= 8'hcd;
+    8'h81: out <= 8'h0c;
+    8'h82: out <= 8'h13;
+    8'h83: out <= 8'hec;
+    8'h84: out <= 8'h5f;
+    8'h85: out <= 8'h97;
+    8'h86: out <= 8'h44;
+    8'h87: out <= 8'h17;
+    8'h88: out <= 8'hc4;
+    8'h89: out <= 8'ha7;
+    8'h8a: out <= 8'h7e;
+    8'h8b: out <= 8'h3d;
+    8'h8c: out <= 8'h64;
+    8'h8d: out <= 8'h5d;
+    8'h8e: out <= 8'h19;
+    8'h8f: out <= 8'h73;
+    8'h90: out <= 8'h60;
+    8'h91: out <= 8'h81;
+    8'h92: out <= 8'h4f;
+    8'h93: out <= 8'hdc;
+    8'h94: out <= 8'h22;
+    8'h95: out <= 8'h2a;
+    8'h96: out <= 8'h90;
+    8'h97: out <= 8'h88;
+    8'h98: out <= 8'h46;
+    8'h99: out <= 8'hee;
+    8'h9a: out <= 8'hb8;
+    8'h9b: out <= 8'h14;
+    8'h9c: out <= 8'hde;
+    8'h9d: out <= 8'h5e;
+    8'h9e: out <= 8'h0b;
+    8'h9f: out <= 8'hdb;
+    8'ha0: out <= 8'he0;
+    8'ha1: out <= 8'h32;
+    8'ha2: out <= 8'h3a;
+    8'ha3: out <= 8'h0a;
+    8'ha4: out <= 8'h49;
+    8'ha5: out <= 8'h06;
+    8'ha6: out <= 8'h24;
+    8'ha7: out <= 8'h5c;
+    8'ha8: out <= 8'hc2;
+    8'ha9: out <= 8'hd3;
+    8'haa: out <= 8'hac;
+    8'hab: out <= 8'h62;
+    8'hac: out <= 8'h91;
+    8'had: out <= 8'h95;
+    8'hae: out <= 8'he4;
+    8'haf: out <= 8'h79;
+    8'hb0: out <= 8'he7;
+    8'hb1: out <= 8'hc8;
+    8'hb2: out <= 8'h37;
+    8'hb3: out <= 8'h6d;
+    8'hb4: out <= 8'h8d;
+    8'hb5: out <= 8'hd5;
+    8'hb6: out <= 8'h4e;
+    8'hb7: out <= 8'ha9;
+    8'hb8: out <= 8'h6c;
+    8'hb9: out <= 8'h56;
+    8'hba: out <= 8'hf4;
+    8'hbb: out <= 8'hea;
+    8'hbc: out <= 8'h65;
+    8'hbd: out <= 8'h7a;
+    8'hbe: out <= 8'hae;
+    8'hbf: out <= 8'h08;
+    8'hc0: out <= 8'hba;
+    8'hc1: out <= 8'h78;
+    8'hc2: out <= 8'h25;
+    8'hc3: out <= 8'h2e;
+    8'hc4: out <= 8'h1c;
+    8'hc5: out <= 8'ha6;
+    8'hc6: out <= 8'hb4;
+    8'hc7: out <= 8'hc6;
+    8'hc8: out <= 8'he8;
+    8'hc9: out <= 8'hdd;
+    8'hca: out <= 8'h74;
+    8'hcb: out <= 8'h1f;
+    8'hcc: out <= 8'h4b;
+    8'hcd: out <= 8'hbd;
+    8'hce: out <= 8'h8b;
+    8'hcf: out <= 8'h8a;
+    8'hd0: out <= 8'h70;
+    8'hd1: out <= 8'h3e;
+    8'hd2: out <= 8'hb5;
+    8'hd3: out <= 8'h66;
+    8'hd4: out <= 8'h48;
+    8'hd5: out <= 8'h03;
+    8'hd6: out <= 8'hf6;
+    8'hd7: out <= 8'h0e;
+    8'hd8: out <= 8'h61;
+    8'hd9: out <= 8'h35;
+    8'hda: out <= 8'h57;
+    8'hdb: out <= 8'hb9;
+    8'hdc: out <= 8'h86;
+    8'hdd: out <= 8'hc1;
+    8'hde: out <= 8'h1d;
+    8'hdf: out <= 8'h9e;
+    8'he0: out <= 8'he1;
+    8'he1: out <= 8'hf8;
+    8'he2: out <= 8'h98;
+    8'he3: out <= 8'h11;
+    8'he4: out <= 8'h69;
+    8'he5: out <= 8'hd9;
+    8'he6: out <= 8'h8e;
+    8'he7: out <= 8'h94;
+    8'he8: out <= 8'h9b;
+    8'he9: out <= 8'h1e;
+    8'hea: out <= 8'h87;
+    8'heb: out <= 8'he9;
+    8'hec: out <= 8'hce;
+    8'hed: out <= 8'h55;
+    8'hee: out <= 8'h28;
+    8'hef: out <= 8'hdf;
+    8'hf0: out <= 8'h8c;
+    8'hf1: out <= 8'ha1;
+    8'hf2: out <= 8'h89;
+    8'hf3: out <= 8'h0d;
+    8'hf4: out <= 8'hbf;
+    8'hf5: out <= 8'he6;
+    8'hf6: out <= 8'h42;
+    8'hf7: out <= 8'h68;
+    8'hf8: out <= 8'h41;
+    8'hf9: out <= 8'h99;
+    8'hfa: out <= 8'h2d;
+    8'hfb: out <= 8'h0f;
+    8'hfc: out <= 8'hb0;
+    8'hfd: out <= 8'h54;
+    8'hfe: out <= 8'hbb;
+    8'hff: out <= 8'h16;
+    endcase
+endmodule
+
+/* S box * x */
+module xS (in, out);
+
+    input [7:0] in;
+    output reg [7:0] out;
+
+    always @ (*)
+    case (in)
+    8'h00: out <= 8'hc6;
+    8'h01: out <= 8'hf8;
+    8'h02: out <= 8'hee;
+    8'h03: out <= 8'hf6;
+    8'h04: out <= 8'hff;
+    8'h05: out <= 8'hd6;
+    8'h06: out <= 8'hde;
+    8'h07: out <= 8'h91;
+    8'h08: out <= 8'h60;
+    8'h09: out <= 8'h02;
+    8'h0a: out <= 8'hce;
+    8'h0b: out <= 8'h56;
+    8'h0c: out <= 8'he7;
+    8'h0d: out <= 8'hb5;
+    8'h0e: out <= 8'h4d;
+    8'h0f: out <= 8'hec;
+    8'h10: out <= 8'h8f;
+    8'h11: out <= 8'h1f;
+    8'h12: out <= 8'h89;
+    8'h13: out <= 8'hfa;
+    8'h14: out <= 8'hef;
+    8'h15: out <= 8'hb2;
+    8'h16: out <= 8'h8e;
+    8'h17: out <= 8'hfb;
+    8'h18: out <= 8'h41;
+    8'h19: out <= 8'hb3;
+    8'h1a: out <= 8'h5f;
+    8'h1b: out <= 8'h45;
+    8'h1c: out <= 8'h23;
+    8'h1d: out <= 8'h53;
+    8'h1e: out <= 8'he4;
+    8'h1f: out <= 8'h9b;
+    8'h20: out <= 8'h75;
+    8'h21: out <= 8'he1;
+    8'h22: out <= 8'h3d;
+    8'h23: out <= 8'h4c;
+    8'h24: out <= 8'h6c;
+    8'h25: out <= 8'h7e;
+    8'h26: out <= 8'hf5;
+    8'h27: out <= 8'h83;
+    8'h28: out <= 8'h68;
+    8'h29: out <= 8'h51;
+    8'h2a: out <= 8'hd1;
+    8'h2b: out <= 8'hf9;
+    8'h2c: out <= 8'he2;
+    8'h2d: out <= 8'hab;
+    8'h2e: out <= 8'h62;
+    8'h2f: out <= 8'h2a;
+    8'h30: out <= 8'h08;
+    8'h31: out <= 8'h95;
+    8'h32: out <= 8'h46;
+    8'h33: out <= 8'h9d;
+    8'h34: out <= 8'h30;
+    8'h35: out <= 8'h37;
+    8'h36: out <= 8'h0a;
+    8'h37: out <= 8'h2f;
+    8'h38: out <= 8'h0e;
+    8'h39: out <= 8'h24;
+    8'h3a: out <= 8'h1b;
+    8'h3b: out <= 8'hdf;
+    8'h3c: out <= 8'hcd;
+    8'h3d: out <= 8'h4e;
+    8'h3e: out <= 8'h7f;
+    8'h3f: out <= 8'hea;
+    8'h40: out <= 8'h12;
+    8'h41: out <= 8'h1d;
+    8'h42: out <= 8'h58;
+    8'h43: out <= 8'h34;
+    8'h44: out <= 8'h36;
+    8'h45: out <= 8'hdc;
+    8'h46: out <= 8'hb4;
+    8'h47: out <= 8'h5b;
+    8'h48: out <= 8'ha4;
+    8'h49: out <= 8'h76;
+    8'h4a: out <= 8'hb7;
+    8'h4b: out <= 8'h7d;
+    8'h4c: out <= 8'h52;
+    8'h4d: out <= 8'hdd;
+    8'h4e: out <= 8'h5e;
+    8'h4f: out <= 8'h13;
+    8'h50: out <= 8'ha6;
+    8'h51: out <= 8'hb9;
+    8'h52: out <= 8'h00;
+    8'h53: out <= 8'hc1;
+    8'h54: out <= 8'h40;
+    8'h55: out <= 8'he3;
+    8'h56: out <= 8'h79;
+    8'h57: out <= 8'hb6;
+    8'h58: out <= 8'hd4;
+    8'h59: out <= 8'h8d;
+    8'h5a: out <= 8'h67;
+    8'h5b: out <= 8'h72;
+    8'h5c: out <= 8'h94;
+    8'h5d: out <= 8'h98;
+    8'h5e: out <= 8'hb0;
+    8'h5f: out <= 8'h85;
+    8'h60: out <= 8'hbb;
+    8'h61: out <= 8'hc5;
+    8'h62: out <= 8'h4f;
+    8'h63: out <= 8'hed;
+    8'h64: out <= 8'h86;
+    8'h65: out <= 8'h9a;
+    8'h66: out <= 8'h66;
+    8'h67: out <= 8'h11;
+    8'h68: out <= 8'h8a;
+    8'h69: out <= 8'he9;
+    8'h6a: out <= 8'h04;
+    8'h6b: out <= 8'hfe;
+    8'h6c: out <= 8'ha0;
+    8'h6d: out <= 8'h78;
+    8'h6e: out <= 8'h25;
+    8'h6f: out <= 8'h4b;
+    8'h70: out <= 8'ha2;
+    8'h71: out <= 8'h5d;
+    8'h72: out <= 8'h80;
+    8'h73: out <= 8'h05;
+    8'h74: out <= 8'h3f;
+    8'h75: out <= 8'h21;
+    8'h76: out <= 8'h70;
+    8'h77: out <= 8'hf1;
+    8'h78: out <= 8'h63;
+    8'h79: out <= 8'h77;
+    8'h7a: out <= 8'haf;
+    8'h7b: out <= 8'h42;
+    8'h7c: out <= 8'h20;
+    8'h7d: out <= 8'he5;
+    8'h7e: out <= 8'hfd;
+    8'h7f: out <= 8'hbf;
+    8'h80: out <= 8'h81;
+    8'h81: out <= 8'h18;
+    8'h82: out <= 8'h26;
+    8'h83: out <= 8'hc3;
+    8'h84: out <= 8'hbe;
+    8'h85: out <= 8'h35;
+    8'h86: out <= 8'h88;
+    8'h87: out <= 8'h2e;
+    8'h88: out <= 8'h93;
+    8'h89: out <= 8'h55;
+    8'h8a: out <= 8'hfc;
+    8'h8b: out <= 8'h7a;
+    8'h8c: out <= 8'hc8;
+    8'h8d: out <= 8'hba;
+    8'h8e: out <= 8'h32;
+    8'h8f: out <= 8'he6;
+    8'h90: out <= 8'hc0;
+    8'h91: out <= 8'h19;
+    8'h92: out <= 8'h9e;
+    8'h93: out <= 8'ha3;
+    8'h94: out <= 8'h44;
+    8'h95: out <= 8'h54;
+    8'h96: out <= 8'h3b;
+    8'h97: out <= 8'h0b;
+    8'h98: out <= 8'h8c;
+    8'h99: out <= 8'hc7;
+    8'h9a: out <= 8'h6b;
+    8'h9b: out <= 8'h28;
+    8'h9c: out <= 8'ha7;
+    8'h9d: out <= 8'hbc;
+    8'h9e: out <= 8'h16;
+    8'h9f: out <= 8'had;
+    8'ha0: out <= 8'hdb;
+    8'ha1: out <= 8'h64;
+    8'ha2: out <= 8'h74;
+    8'ha3: out <= 8'h14;
+    8'ha4: out <= 8'h92;
+    8'ha5: out <= 8'h0c;
+    8'ha6: out <= 8'h48;
+    8'ha7: out <= 8'hb8;
+    8'ha8: out <= 8'h9f;
+    8'ha9: out <= 8'hbd;
+    8'haa: out <= 8'h43;
+    8'hab: out <= 8'hc4;
+    8'hac: out <= 8'h39;
+    8'had: out <= 8'h31;
+    8'hae: out <= 8'hd3;
+    8'haf: out <= 8'hf2;
+    8'hb0: out <= 8'hd5;
+    8'hb1: out <= 8'h8b;
+    8'hb2: out <= 8'h6e;
+    8'hb3: out <= 8'hda;
+    8'hb4: out <= 8'h01;
+    8'hb5: out <= 8'hb1;
+    8'hb6: out <= 8'h9c;
+    8'hb7: out <= 8'h49;
+    8'hb8: out <= 8'hd8;
+    8'hb9: out <= 8'hac;
+    8'hba: out <= 8'hf3;
+    8'hbb: out <= 8'hcf;
+    8'hbc: out <= 8'hca;
+    8'hbd: out <= 8'hf4;
+    8'hbe: out <= 8'h47;
+    8'hbf: out <= 8'h10;
+    8'hc0: out <= 8'h6f;
+    8'hc1: out <= 8'hf0;
+    8'hc2: out <= 8'h4a;
+    8'hc3: out <= 8'h5c;
+    8'hc4: out <= 8'h38;
+    8'hc5: out <= 8'h57;
+    8'hc6: out <= 8'h73;
+    8'hc7: out <= 8'h97;
+    8'hc8: out <= 8'hcb;
+    8'hc9: out <= 8'ha1;
+    8'hca: out <= 8'he8;
+    8'hcb: out <= 8'h3e;
+    8'hcc: out <= 8'h96;
+    8'hcd: out <= 8'h61;
+    8'hce: out <= 8'h0d;
+    8'hcf: out <= 8'h0f;
+    8'hd0: out <= 8'he0;
+    8'hd1: out <= 8'h7c;
+    8'hd2: out <= 8'h71;
+    8'hd3: out <= 8'hcc;
+    8'hd4: out <= 8'h90;
+    8'hd5: out <= 8'h06;
+    8'hd6: out <= 8'hf7;
+    8'hd7: out <= 8'h1c;
+    8'hd8: out <= 8'hc2;
+    8'hd9: out <= 8'h6a;
+    8'hda: out <= 8'hae;
+    8'hdb: out <= 8'h69;
+    8'hdc: out <= 8'h17;
+    8'hdd: out <= 8'h99;
+    8'hde: out <= 8'h3a;
+    8'hdf: out <= 8'h27;
+    8'he0: out <= 8'hd9;
+    8'he1: out <= 8'heb;
+    8'he2: out <= 8'h2b;
+    8'he3: out <= 8'h22;
+    8'he4: out <= 8'hd2;
+    8'he5: out <= 8'ha9;
+    8'he6: out <= 8'h07;
+    8'he7: out <= 8'h33;
+    8'he8: out <= 8'h2d;
+    8'he9: out <= 8'h3c;
+    8'hea: out <= 8'h15;
+    8'heb: out <= 8'hc9;
+    8'hec: out <= 8'h87;
+    8'hed: out <= 8'haa;
+    8'hee: out <= 8'h50;
+    8'hef: out <= 8'ha5;
+    8'hf0: out <= 8'h03;
+    8'hf1: out <= 8'h59;
+    8'hf2: out <= 8'h09;
+    8'hf3: out <= 8'h1a;
+    8'hf4: out <= 8'h65;
+    8'hf5: out <= 8'hd7;
+    8'hf6: out <= 8'h84;
+    8'hf7: out <= 8'hd0;
+    8'hf8: out <= 8'h82;
+    8'hf9: out <= 8'h29;
+    8'hfa: out <= 8'h5a;
+    8'hfb: out <= 8'h1e;
+    8'hfc: out <= 8'h7b;
+    8'hfd: out <= 8'ha8;
+    8'hfe: out <= 8'h6d;
+    8'hff: out <= 8'h2c;
+    endcase
+endmodule
+
+

misc_reviewed/stat/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

misc_reviewed/stat/stat.ys

+read_verilog ../top.v
+proc
+tee -o result.log stat

misc_reviewed/stat/stat_cant_find_module_fail.pat

+ERROR: Can't find module uut.

misc_reviewed/stat/stat_cant_find_module_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log stat -top uut

misc_reviewed/stat/stat_cant_open_lib_file_fail.pat

+ERROR: Can't open liberty file `lib.lib': No such file or directory

misc_reviewed/stat/stat_cant_open_lib_file_fail.ys

+read_verilog ../top.v
+tee -o result.log stat -liberty lib.lib

misc_reviewed/stat/stat_liberty.ys

+read_verilog ../top.v
+tee -o result.log stat -liberty ../lib.lib

misc_reviewed/stat/stat_mem.ys

+read_verilog ../top_mem.v
+hierarchy -top top
+proc
+memory -nomap
+synth_xilinx
+tee -o result.log stat -tech xilinx

misc_reviewed/stat/stat_tech_cmos.ys

+read_verilog ../top.v
+synth_xilinx
+tee -o result.log stat -tech cmos

misc_reviewed/stat/stat_tech_mem.ys

+read_verilog ../top_mem.v
+hierarchy -top top
+proc
+memory -nomap
+synth_xilinx -nodram
+tee -o result.log stat -tech xilinx

misc_reviewed/stat/stat_tech_xilinx.ys

+read_verilog ../top.v
+synth_xilinx
+tee -o result.log stat -tech xilinx

misc_reviewed/stat/stat_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log stat -top top

misc_reviewed/stat/stat_unsupported_tech_fail.pat

+ERROR: Unsupported technology: 'ice40'

misc_reviewed/stat/stat_unsupported_tech_fail.ys

+read_verilog ../top.v
+synth_xilinx
+tee -o result.log stat -tech ice40

misc_reviewed/stat/stat_width.ys

+read_verilog ../top.v
+tee -o result.log stat -width
+tee -o result.log stat -width $add_8

misc_reviewed/stat/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/stat/top_mem.v

+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
+*/
+module top (din, write_en, waddr, wclk, raddr, rclk, dout);
+parameter addr_width = 6;
+parameter data_width = 6;
+input [addr_width-1:0] waddr, raddr;
+input [data_width-1:0] din;
+input write_en, wclk, rclk;
+output [data_width-1:0] dout;
+reg [data_width-1:0] dout;
+reg [data_width-1:0] mem [(1<<addr_width)-1:0]
+/* synthesis syn_ramstyle = "no_rw_check" */ ;
+always @(posedge wclk) // Write memory.
+begin
+if (write_en)
+mem[waddr] <= din; // Using write address bus.
+end
+always @(posedge rclk) // Read memory.
+begin
+dout <= mem[raddr]; // Using read address bus.
+end
+endmodule

misc_reviewed/supercover/supercover.pat

+cell $cover

misc_reviewed/supercover/supercover.ys

+read_verilog ../top.v
+proc
+supercover
+tee -o result.out dump

misc_reviewed/supercover/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+ initial A = 0;
+ initial cout = 0;
+
+
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/tcl/tcl.tcl

+puts "Execute tcl script!"

misc_reviewed/tcl/tcl.ys

+tee -o result.log tcl ../tcl.tcl

misc_reviewed/tcl/top.v

+(* black_box *) module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/tee/tee.ys

+read_verilog ../top.v
+proc
+tee -q -o result.log -a result2.log ls

misc_reviewed/tee/tee_a_cant_create_file_fail.pat

+ERROR: Can't create file ./tt/result.log.

misc_reviewed/tee/tee_a_cant_create_file_fail.ys

+read_verilog ../top.v
+proc
+tee -a ./tt/result.log ls

misc_reviewed/tee/tee_o_cant_create_file_fail.pat

+ERROR: Can't create file ./tt/result.log.

misc_reviewed/tee/tee_o_cant_create_file_fail.ys

+read_verilog ../top.v
+proc
+tee -o ./tt/result.log ls

misc_reviewed/tee/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/test_abcloop/test_abcloop.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop

misc_reviewed/test_abcloop/test_abcloop_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop -n 50

misc_reviewed/test_abcloop/test_abcloop_s.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_abcloop -s 50

misc_reviewed/test_abcloop/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/test_autotb/test_autotb.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_autotb

misc_reviewed/test_autotb/test_autotb_file.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_autotb t.v

misc_reviewed/test_autotb/test_autotb_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_autotb -n 200 t.v

misc_reviewed/test_autotb/test_autotb_seed.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_autotb -seed a

misc_reviewed/test_autotb/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/test_cell/gold.v

+module gold
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/test_cell/ilang.ilang

+# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
+autoidx 169
+attribute \top 1
+attribute \src "gold.v:1"
+module \gold
+  wire $abc$163$new_n6_
+  wire $abc$163$new_n7_
+  wire $abc$163$new_n9_
+  attribute \src "gold.v:7"
+  wire output 4 \A
+  attribute \src "gold.v:5"
+  wire input 3 \cin
+  attribute \src "gold.v:8"
+  wire output 5 \cout
+  attribute \src "gold.v:3"
+  wire input 1 \x
+  attribute \src "gold.v:4"
+  wire input 2 \y
+  cell $_NOT_ $abc$163$auto$blifparse.cc:371:parse_blif$164
+    connect \A \y
+    connect \Y $abc$163$new_n6_
+  end
+  cell $_XNOR_ $abc$163$auto$blifparse.cc:371:parse_blif$165
+    connect \A \cin
+    connect \B \x
+    connect \Y $abc$163$new_n7_
+  end
+  cell $_XOR_ $abc$163$auto$blifparse.cc:371:parse_blif$166
+    connect \A $abc$163$new_n7_
+    connect \B $abc$163$new_n6_
+    connect \Y \A
+  end
+  cell $_NAND_ $abc$163$auto$blifparse.cc:371:parse_blif$167
+    connect \A \cin
+    connect \B \x
+    connect \Y $abc$163$new_n9_
+  end
+  cell $_OAI3_ $abc$163$auto$blifparse.cc:371:parse_blif$168
+    connect \A $abc$163$new_n7_
+    connect \B $abc$163$new_n6_
+    connect \C $abc$163$new_n9_
+    connect \Y \cout
+  end
+end

misc_reviewed/test_cell/simlib.v

+
+module \$add (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+generate
+	if (A_SIGNED && B_SIGNED) begin:BLOCK1
+		assign Y = $signed(A) + $signed(B);
+	end else begin:BLOCK2
+		assign Y = A + B;
+	end
+endgenerate
+
+endmodule

misc_reviewed/test_cell/test_cell.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $add

misc_reviewed/test_cell/test_cell_aigmap.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -aigmap $add

misc_reviewed/test_cell/test_cell_alu.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $alu

misc_reviewed/test_cell/test_cell_cell_type_not_supported_fail.pat

+ERROR: The cell type `$_XOR_' is currently not supported. Try one of these:

misc_reviewed/test_cell/test_cell_cell_type_not_supported_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $_XOR_

misc_reviewed/test_cell/test_cell_const.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -const $add

misc_reviewed/test_cell/test_cell_div.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 $div $mod

misc_reviewed/test_cell/test_cell_dont_spec_cell_type_with_f_fail.pat

+ERROR: Do not specify any cell types when using -f.

misc_reviewed/test_cell/test_cell_dont_spec_cell_type_with_f_fail.ys

+read_verilog ../gold.v
+synth -top gold
+write_ilang ilang.ilang
+design -reset
+tee -o result.log test_cell -f ilang.ilang $add

misc_reviewed/test_cell/test_cell_edges.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -v -edges $add

misc_reviewed/test_cell/test_cell_f.ys

+read_verilog ../gold.v
+synth -top gold
+write_ilang ilang.ilang
+design -reset
+tee -o result.log test_cell -f ilang.ilang

misc_reviewed/test_cell/test_cell_fa.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $fa

misc_reviewed/test_cell/test_cell_failed_to_open_fail.pat

+ERROR: Failed to open output file `tt/vlog.v'.

misc_reviewed/test_cell/test_cell_failed_to_open_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -vlog tt/vlog.v

misc_reviewed/test_cell/test_cell_lcu.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $lcu

misc_reviewed/test_cell/test_cell_lut.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $lut

misc_reviewed/test_cell/test_cell_macc.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 $macc

misc_reviewed/test_cell/test_cell_map.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 2 -map +/techmap.v $add

misc_reviewed/test_cell/test_cell_mux_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $mux

misc_reviewed/test_cell/test_cell_muxdiv.ys

+read_verilog ../top_div.v
+synth -top top
+tee -o result.log test_cell -muxdiv $div

misc_reviewed/test_cell/test_cell_n.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -n 50 $add

misc_reviewed/test_cell/test_cell_no_cell_t_specified_fail.pat

+ERROR: No cell type to test specified.

misc_reviewed/test_cell/test_cell_no_cell_t_specified_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell

misc_reviewed/test_cell/test_cell_noeval.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -noeval $add

misc_reviewed/test_cell/test_cell_nosat.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -nosat $add

misc_reviewed/test_cell/test_cell_pmux_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $pmux

misc_reviewed/test_cell/test_cell_s.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -s 50 $add

misc_reviewed/test_cell/test_cell_scr.ys

+proc

misc_reviewed/test_cell/test_cell_script.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -script ../test_cell_scr.ys $add

misc_reviewed/test_cell/test_cell_simlib.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -simlib $add

misc_reviewed/test_cell/test_cell_sop.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell $sop

misc_reviewed/test_cell/test_cell_unexpected_opt_fail.pat

+ERROR: Unexpected option: -scd

misc_reviewed/test_cell/test_cell_unexpected_opt_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -scd

misc_reviewed/test_cell/test_cell_v.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -v $add

misc_reviewed/test_cell/test_cell_vlog.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -vlog vlog.v $add

misc_reviewed/test_cell/test_cell_w.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log test_cell -w pref $add

misc_reviewed/test_cell/test_cell_wo_synth.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_cell $add

misc_reviewed/test_cell/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/test_cell/top_div.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y / x;
+
+endmodule

misc_reviewed/torder/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/torder/torder.pat

+module top
+  cell $add$../top.v:12$1
+  cell $add$../top.v:12$2

misc_reviewed/torder/torder.ys

+read_verilog ../top.v
+tee -o result.out torder

misc_reviewed/torder/torder_noautostop.pat

+module top
+  cell $add$../top.v:12$1
+  cell $add$../top.v:12$2

misc_reviewed/torder/torder_noautostop.ys

+read_verilog ../top.v
+tee -o result.out torder -noautostop

misc_reviewed/torder/torder_stop.pat

+module top
+  cell $add$../top.v:12$1
+  cell $add$../top.v:12$2

misc_reviewed/torder/torder_stop.ys

+read_verilog ../top.v
+tee -o result.out torder -stop $add A

misc_reviewed/trace/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/trace/top_del.v

+module top
+(
+ input x
+ );
+
+endmodule
+
+module top1
+(
+ input x
+ );
+
+endmodule

misc_reviewed/trace/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

misc_reviewed/trace/trace.ys

+read_verilog ../top.v
+ trace synth -top top
+proc
+ trace synth -top top
+synth
+ trace synth -top top

misc_reviewed/trace/trace_add.ys

+read_verilog ../top.v
+trace add -mod top3 -wire w 0
+ trace synth -top top

misc_reviewed/trace/trace_del.ys

+read_verilog ../top_del.v
+trace delete -port top1/*
+ trace synth -top top

misc_reviewed/trace/trace_mem.ys

+read_verilog ../top_mem.v
+ trace synth -top top
+proc
+memory
+ trace synth -top top
+synth
+ trace synth -top top

misc_reviewed/wbflip/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/wbflip/wbflip.ys

+read_verilog ../top.v
+proc
+wbflip

misc_reviewed/wbflip/wbflip_top.ys

+read_verilog ../top.v
+proc
+wbflip top

misc_reviewed/write_file/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/write_file/write_file.ys

+read_verilog ../top.v
+tee -o result.log write_file out.v ../top.v

misc_reviewed/write_file/write_file_a.ys

+read_verilog ../top.v
+tee -o result.log write_file -a out.v ../top.v

misc_reviewed/write_file/write_file_a_missing_name_fail.pat

+ERROR: Missing output filename.

misc_reviewed/write_file/write_file_a_missing_name_fail.ys

+read_verilog ../top.v
+tee -o result.log write_file -a

misc_reviewed/write_file/write_file_missing_name_fail.pat

+ERROR: Missing output filename.

misc_reviewed/write_file/write_file_missing_name_fail.ys

+read_verilog ../top.v
+tee -o result.log write_file