Merge pull request #5 from SergeyDegtyar/master

Add tests for "II architecture" and "III backends" and "IV frontends"

Makefile

 
-SUBDIRS := bigsim simple
+SUBDIRS := architecture backends bigsim simple
 
 ifeq ($(VERIFIC),1)
 export VERIFIC=1

architecture/.gitignore

+/.stamp

architecture/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+$(foreach design,$(1),
+$(foreach script,$(2),
+work:: $(design)/work_$(script)/.stamp
+
+$(design)/work_$(script)/.stamp:
+	bash run.sh $(design) $(script)
+
+clean::
+	rm -rf $(design)/work_$(script)
+))
+endef
+
+#achronix (in the code '-flatten' but in the help '-noflatten')
+$(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_achronix_vout synth_achronix_run synth_achronix_noflatten synth_achronix_retime))
+
+#coolrunner2
+$(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
+
+#easic
+#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
+
+#ecp5
+$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr))
+
+#gowin
+$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime))
+
+#ice40
+$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr))
+
+#intel (in the code '-flatten' but in the help '-noflatten')
+$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
+$(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv  ))
+$(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive   ))
+#../../../../../techlibs/intel/cyclonev/cells_sim.v:88: error: Unable to bind wire/reg/memory `upper_mask_value' in `testbench.uut._05_.lut5'
+#$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
+$(eval $(call template,synth_intel_cyclone10,synth_intel_cyclone10  ))
+$(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
+
+#sf2
+$(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime ))
+
+#xilinx
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr))
+
+#greenpak4
+$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
+
+.PHONY: all clean

architecture/common.v

+module assert_dff(input clk, input test, input pat);
+    always @(posedge clk)
+    begin
+        if (test != pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time);
+            $stop;
+        end
+    end
+endmodule 
+
+module assert_tri(input en, input A, input B);
+    always @(posedge en)
+    begin
+        //#1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_Z(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A === 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_comb(input A, input B);
+    always @(*)
+    begin
+        #1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule

architecture/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+if [ "$1" = "synth_ecp5" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
+elif [ "$1" = "synth_achronix" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
+elif [ "$1" = "synth_coolrunner2" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
+elif [ "$1" = "synth_gowin" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
+elif [ "$1" = "synth_ice40" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
+elif [ "$1" = "synth_intel" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/max10/cells_sim.v
+elif [ "$1" = "synth_intel_a10gx" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/a10gx/cells_sim.v
+elif [ "$1" = "synth_intel_cycloneiv" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneiv/cells_sim.v
+elif [ "$1" = "synth_intel_cycloneive" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneive/cells_sim.v
+elif [ "$1" = "synth_intel_cyclone10" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclone10/cells_sim.v
+elif [ "$1" = "synth_intel_cyclonev" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclonev/cells_sim.v
+elif [ "$1" = "synth_sf2" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/sf2/cells_sim.v
+elif [ "$1" = "synth_xilinx" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
+elif [ "$1" = "synth_greenpak4" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
+else 
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
+fi
+
+if ! vvp -N testbench > testbench.log 2>&1; then
+	grep 'ERROR' testbench.log
+	echo fail > ${1}_${2}.status
+elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

architecture/scripts/synth_achronix.ys

+read_verilog ../top.v
+synth_achronix
+write_verilog synth.v 

architecture/scripts/synth_achronix_noflatten.ys

+read_verilog ../top.v
+synth_achronix -flatten
+write_verilog synth.v 

architecture/scripts/synth_achronix_retime.ys

+read_verilog ../top.v
+synth_achronix -retime
+write_verilog synth.v 

architecture/scripts/synth_achronix_run.ys

+read_verilog ../top.v
+synth_achronix -run begin:vout
+write_verilog synth.v 

architecture/scripts/synth_achronix_top.ys

+read_verilog ../top.v
+synth_achronix -top top
+write_verilog synth.v 

architecture/scripts/synth_achronix_vout.ys

+read_verilog ../top.v
+synth_achronix -vout vout.v
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2.ys

+read_verilog ../top.v
+synth_coolrunner2
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_noflatten.ys

+read_verilog ../top.v
+synth_coolrunner2 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_retime.ys

+read_verilog ../top.v
+synth_coolrunner2 -retime
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_run.ys

+read_verilog ../top.v
+synth_coolrunner2 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_top.ys

+read_verilog ../top.v
+synth_coolrunner2 -top top
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_vlog.ys

+read_verilog ../top.v
+synth_easic -vlog vlog.v
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_vout.ys

+read_verilog ../top.v
+synth_coolrunner2 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_easic.ys

+read_verilog ../top.v
+synth_easic
+write_verilog synth.v 

architecture/scripts/synth_easic_etools.ys

+read_verilog ../top.v
+synth_easic -etools
+write_verilog synth.v 

architecture/scripts/synth_easic_noflatten.ys

+read_verilog ../top.v
+synth_easic -noflatten
+write_verilog synth.v 

architecture/scripts/synth_easic_retime.ys

+read_verilog ../top.v
+synth_easic -retime
+write_verilog synth.v 

architecture/scripts/synth_easic_run.ys

+read_verilog ../top.v
+synth_easic -run begin:vlog
+write_verilog synth.v 

architecture/scripts/synth_easic_top.ys

+read_verilog ../top.v
+synth_easic -top top
+write_verilog synth.v 

architecture/scripts/synth_ecp5.ys

+read_verilog ../top.v
+synth_ecp5
+write_verilog synth.v 

architecture/scripts/synth_ecp5_abc2.ys

+read_verilog ../top.v
+synth_ecp5 -abc2
+write_verilog synth.v 

architecture/scripts/synth_ecp5_blif.ys

+read_verilog ../top.v
+synth_ecp5 -blif blif.blif
+write_verilog synth.v 

architecture/scripts/synth_ecp5_edif.ys

+read_verilog ../top.v
+synth_ecp5 -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_ecp5_flatten.ys

+read_verilog ../top.v
+synth_ecp5 -flatten
+write_verilog synth.v 

architecture/scripts/synth_ecp5_json.ys

+read_verilog ../top.v
+synth_ecp5 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nobram.ys

+read_verilog ../top.v
+synth_ecp5 -nobram
+write_verilog synth.v 

architecture/scripts/synth_ecp5_noccu2.ys

+read_verilog ../top.v
+synth_ecp5 -noccu2
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nodffe.ys

+read_verilog ../top.v
+synth_ecp5 -nodffe
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nodram.ys

+read_verilog ../top.v
+synth_ecp5 -nodram
+write_verilog synth.v 

architecture/scripts/synth_ecp5_noflatten.ys

+read_verilog ../top.v
+synth_ecp5 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nomux.ys

+read_verilog ../top.v
+synth_ecp5 -nomux
+write_verilog synth.v 

architecture/scripts/synth_ecp5_retime.ys

+read_verilog ../top.v
+synth_ecp5 -retime
+write_verilog synth.v 

architecture/scripts/synth_ecp5_run.ys

+read_verilog ../top.v
+synth_ecp5 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_ecp5_top.ys

+read_verilog ../top.v
+synth_ecp5 -top top
+write_verilog synth.v 

architecture/scripts/synth_ecp5_vpr.ys

+read_verilog ../top.v
+synth_ecp5 -vpr
+write_verilog synth.v 

architecture/scripts/synth_gowin.ys

+read_verilog ../top.v
+synth_gowin
+write_verilog synth.v 

architecture/scripts/synth_gowin_retime.ys

+read_verilog ../top.v
+synth_gowin -retime
+write_verilog synth.v 

architecture/scripts/synth_gowin_run.ys

+read_verilog ../top.v
+synth_gowin -run begin:vout
+write_verilog synth.v 

architecture/scripts/synth_gowin_top.ys

+read_verilog ../top.v
+synth_gowin -top top
+write_verilog synth.v 

architecture/scripts/synth_gowin_vout.ys

+read_verilog ../top.v
+synth_gowin -vout vout.v
+write_verilog synth.v 

architecture/scripts/synth_greenpak4.ys

+read_verilog ../top.v
+synth_greenpak4
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_json.ys

+read_verilog ../top.v
+synth_greenpak4 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_noflatten.ys

+read_verilog ../top.v
+synth_greenpak4 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_part140.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46140V
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_part620.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46620V
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_part621.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46621V
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_retime.ys

+read_verilog ../top.v
+synth_greenpak4 -retime
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_run.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_top.ys

+read_verilog ../top.v
+synth_greenpak4 -top top
+write_verilog synth.v 

architecture/scripts/synth_ice40.ys

+read_verilog ../top.v
+synth_ice40
+write_verilog synth.v 

architecture/scripts/synth_ice40_abc2.ys

+read_verilog ../top.v
+synth_ice40 -abc2
+write_verilog synth.v 

architecture/scripts/synth_ice40_blif.ys

+read_verilog ../top.v
+synth_ice40 -blif blif.blif
+write_verilog synth.v 

architecture/scripts/synth_ice40_edif.ys

+read_verilog ../top.v
+synth_ice40 -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_ice40_flatten.ys

+read_verilog ../top.v
+synth_ice40 -flatten
+write_verilog synth.v 

architecture/scripts/synth_ice40_json.ys

+read_verilog ../top.v
+synth_ice40 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_ice40_nobram.ys

+read_verilog ../top.v
+synth_ice40 -nobram
+write_verilog synth.v 

architecture/scripts/synth_ice40_nocarry.ys

+read_verilog ../top.v
+synth_ice40 -nocarry
+write_verilog synth.v 

architecture/scripts/synth_ice40_nodffe.ys

+read_verilog ../top.v
+synth_ice40 -nodffe
+write_verilog synth.v 

architecture/scripts/synth_ice40_noflatten.ys

+read_verilog ../top.v
+synth_ice40 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_ice40_retime.ys

+read_verilog ../top.v
+synth_ice40 -retime
+write_verilog synth.v 

architecture/scripts/synth_ice40_run.ys

+read_verilog ../top.v
+synth_ice40 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_ice40_top.ys

+read_verilog ../top.v
+synth_ice40 -top top
+write_verilog synth.v 

architecture/scripts/synth_ice40_vpr.ys

+read_verilog ../top.v
+synth_ice40 -vpr
+write_verilog synth.v 

architecture/scripts/synth_intel.ys

+read_verilog ../top.v
+synth_intel
+write_verilog synth.v 

architecture/scripts/synth_intel_a10gx.ys

+read_verilog ../top.v
+synth_intel -family a10gx
+write_verilog synth.v 

architecture/scripts/synth_intel_cyclone10.ys

+read_verilog ../top.v
+synth_intel -family cyclone10
+write_verilog synth.v 

architecture/scripts/synth_intel_cycloneiv.ys

+read_verilog ../top.v
+synth_intel -family cycloneiv
+write_verilog synth.v 

architecture/scripts/synth_intel_cycloneive.ys

+read_verilog ../top.v
+synth_intel -family cycloneive
+write_verilog synth.v 

architecture/scripts/synth_intel_cyclonev.ys

+read_verilog ../top.v
+synth_intel -family cyclonev
+write_verilog synth.v 

architecture/scripts/synth_intel_max10.ys

+read_verilog ../top.v
+synth_intel -family max10
+write_verilog synth.v 

architecture/scripts/synth_intel_nobram.ys

+read_verilog ../top.v
+synth_intel -nobram
+write_verilog synth.v 

architecture/scripts/synth_intel_noflatten.ys

+read_verilog ../top.v
+synth_intel -flatten
+write_verilog synth.v 

architecture/scripts/synth_intel_noiopads.ys

+read_verilog ../top.v
+synth_intel -noiopads
+write_verilog synth.v 

architecture/scripts/synth_intel_retime.ys

+read_verilog ../top.v
+synth_intel -retime
+write_verilog synth.v 

architecture/scripts/synth_intel_run.ys

+read_verilog ../top.v
+synth_intel -run family:vpr
+write_verilog synth.v 

architecture/scripts/synth_intel_top.ys

+read_verilog ../top.v
+synth_intel -top top
+write_verilog synth.v 

architecture/scripts/synth_intel_vpr.ys

+read_verilog ../top.v
+synth_intel -vpr vpr.vpr
+write_verilog synth.v 

architecture/scripts/synth_intel_vqm.ys

+read_verilog ../top.v
+synth_intel -vqm vqm.vqm
+write_verilog synth.v 

architecture/scripts/synth_sf2.ys

+read_verilog ../top.v
+synth_sf2
+write_verilog synth.v 

architecture/scripts/synth_sf2_edif.ys

+read_verilog ../top.v
+synth_sf2 -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_sf2_json.ys

+read_verilog ../top.v
+synth_sf2 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_sf2_noflatten.ys

+read_verilog ../top.v
+synth_sf2 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_sf2_retime.ys

+read_verilog ../top.v
+synth_sf2 -retime
+write_verilog synth.v 

architecture/scripts/synth_sf2_run.ys

+read_verilog ../top.v
+synth_sf2 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_sf2_top.ys

+read_verilog ../top.v
+synth_sf2 -top top
+write_verilog synth.v 

architecture/scripts/synth_xilinx.ys

+read_verilog ../top.v
+synth_xilinx
+write_verilog synth.v 

architecture/scripts/synth_xilinx_blif.ys

+read_verilog ../top.v
+synth_xilinx -blif blif.blif
+write_verilog synth.v 

architecture/scripts/synth_xilinx_edif.ys

+read_verilog ../top.v
+synth_xilinx -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_xilinx_flatten.ys

+read_verilog ../top.v
+synth_xilinx -flatten
+write_verilog synth.v 

architecture/scripts/synth_xilinx_retime.ys

+read_verilog ../top.v
+synth_xilinx -retime
+write_verilog synth.v 

architecture/scripts/synth_xilinx_run.ys

+read_verilog ../top.v
+synth_xilinx -run begin:blif
+write_verilog synth.v 

architecture/scripts/synth_xilinx_top.ys

+read_verilog ../top.v
+synth_xilinx -top top
+write_verilog synth.v 

architecture/scripts/synth_xilinx_vpr.ys

+read_verilog ../top.v
+synth_xilinx -vpr
+write_verilog synth.v 

architecture/synth_achronix/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_achronix/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule