Merge pull request #5 from SergeyDegtyar/master

Add tests for "II architecture" and "III backends" and "IV frontends"

Makefile

 
-SUBDIRS := bigsim simple
+SUBDIRS := architecture backends bigsim simple
 
 ifeq ($(VERIFIC),1)
 export VERIFIC=1

architecture/.gitignore

+/.stamp

architecture/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+$(foreach design,$(1),
+$(foreach script,$(2),
+work:: $(design)/work_$(script)/.stamp
+
+$(design)/work_$(script)/.stamp:
+	bash run.sh $(design) $(script)
+
+clean::
+	rm -rf $(design)/work_$(script)
+))
+endef
+
+#achronix (in the code '-flatten' but in the help '-noflatten')
+$(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_achronix_vout synth_achronix_run synth_achronix_noflatten synth_achronix_retime))
+
+#coolrunner2
+$(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
+
+#easic
+#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
+
+#ecp5
+$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr))
+
+#gowin
+$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime))
+
+#ice40
+$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr))
+
+#intel (in the code '-flatten' but in the help '-noflatten')
+$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
+$(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv  ))
+$(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive   ))
+#../../../../../techlibs/intel/cyclonev/cells_sim.v:88: error: Unable to bind wire/reg/memory `upper_mask_value' in `testbench.uut._05_.lut5'
+#$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
+$(eval $(call template,synth_intel_cyclone10,synth_intel_cyclone10  ))
+$(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
+
+#sf2
+$(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime ))
+
+#xilinx
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr))
+
+#greenpak4
+$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
+
+.PHONY: all clean

architecture/common.v

+module assert_dff(input clk, input test, input pat);
+    always @(posedge clk)
+    begin
+        if (test != pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time);
+            $stop;
+        end
+    end
+endmodule 
+
+module assert_tri(input en, input A, input B);
+    always @(posedge en)
+    begin
+        //#1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_Z(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A === 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_comb(input A, input B);
+    always @(*)
+    begin
+        #1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule

architecture/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+if [ "$1" = "synth_ecp5" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
+elif [ "$1" = "synth_achronix" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
+elif [ "$1" = "synth_coolrunner2" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
+elif [ "$1" = "synth_gowin" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
+elif [ "$1" = "synth_ice40" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
+elif [ "$1" = "synth_intel" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/max10/cells_sim.v
+elif [ "$1" = "synth_intel_a10gx" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/a10gx/cells_sim.v
+elif [ "$1" = "synth_intel_cycloneiv" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneiv/cells_sim.v
+elif [ "$1" = "synth_intel_cycloneive" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneive/cells_sim.v
+elif [ "$1" = "synth_intel_cyclone10" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclone10/cells_sim.v
+elif [ "$1" = "synth_intel_cyclonev" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclonev/cells_sim.v
+elif [ "$1" = "synth_sf2" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/sf2/cells_sim.v
+elif [ "$1" = "synth_xilinx" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
+elif [ "$1" = "synth_greenpak4" ]; then
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
+else 
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
+fi
+
+if ! vvp -N testbench > testbench.log 2>&1; then
+	grep 'ERROR' testbench.log
+	echo fail > ${1}_${2}.status
+elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

architecture/scripts/synth_achronix.ys

+read_verilog ../top.v
+synth_achronix
+write_verilog synth.v 

architecture/scripts/synth_achronix_noflatten.ys

+read_verilog ../top.v
+synth_achronix -flatten
+write_verilog synth.v 

architecture/scripts/synth_achronix_retime.ys

+read_verilog ../top.v
+synth_achronix -retime
+write_verilog synth.v 

architecture/scripts/synth_achronix_run.ys

+read_verilog ../top.v
+synth_achronix -run begin:vout
+write_verilog synth.v 

architecture/scripts/synth_achronix_top.ys

+read_verilog ../top.v
+synth_achronix -top top
+write_verilog synth.v 

architecture/scripts/synth_achronix_vout.ys

+read_verilog ../top.v
+synth_achronix -vout vout.v
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2.ys

+read_verilog ../top.v
+synth_coolrunner2
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_noflatten.ys

+read_verilog ../top.v
+synth_coolrunner2 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_retime.ys

+read_verilog ../top.v
+synth_coolrunner2 -retime
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_run.ys

+read_verilog ../top.v
+synth_coolrunner2 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_top.ys

+read_verilog ../top.v
+synth_coolrunner2 -top top
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_vlog.ys

+read_verilog ../top.v
+synth_easic -vlog vlog.v
+write_verilog synth.v 

architecture/scripts/synth_coolrunner2_vout.ys

+read_verilog ../top.v
+synth_coolrunner2 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_easic.ys

+read_verilog ../top.v
+synth_easic
+write_verilog synth.v 

architecture/scripts/synth_easic_etools.ys

+read_verilog ../top.v
+synth_easic -etools
+write_verilog synth.v 

architecture/scripts/synth_easic_noflatten.ys

+read_verilog ../top.v
+synth_easic -noflatten
+write_verilog synth.v 

architecture/scripts/synth_easic_retime.ys

+read_verilog ../top.v
+synth_easic -retime
+write_verilog synth.v 

architecture/scripts/synth_easic_run.ys

+read_verilog ../top.v
+synth_easic -run begin:vlog
+write_verilog synth.v 

architecture/scripts/synth_easic_top.ys

+read_verilog ../top.v
+synth_easic -top top
+write_verilog synth.v 

architecture/scripts/synth_ecp5.ys

+read_verilog ../top.v
+synth_ecp5
+write_verilog synth.v 

architecture/scripts/synth_ecp5_abc2.ys

+read_verilog ../top.v
+synth_ecp5 -abc2
+write_verilog synth.v 

architecture/scripts/synth_ecp5_blif.ys

+read_verilog ../top.v
+synth_ecp5 -blif blif.blif
+write_verilog synth.v 

architecture/scripts/synth_ecp5_edif.ys

+read_verilog ../top.v
+synth_ecp5 -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_ecp5_flatten.ys

+read_verilog ../top.v
+synth_ecp5 -flatten
+write_verilog synth.v 

architecture/scripts/synth_ecp5_json.ys

+read_verilog ../top.v
+synth_ecp5 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nobram.ys

+read_verilog ../top.v
+synth_ecp5 -nobram
+write_verilog synth.v 

architecture/scripts/synth_ecp5_noccu2.ys

+read_verilog ../top.v
+synth_ecp5 -noccu2
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nodffe.ys

+read_verilog ../top.v
+synth_ecp5 -nodffe
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nodram.ys

+read_verilog ../top.v
+synth_ecp5 -nodram
+write_verilog synth.v 

architecture/scripts/synth_ecp5_noflatten.ys

+read_verilog ../top.v
+synth_ecp5 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_ecp5_nomux.ys

+read_verilog ../top.v
+synth_ecp5 -nomux
+write_verilog synth.v 

architecture/scripts/synth_ecp5_retime.ys

+read_verilog ../top.v
+synth_ecp5 -retime
+write_verilog synth.v 

architecture/scripts/synth_ecp5_run.ys

+read_verilog ../top.v
+synth_ecp5 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_ecp5_top.ys

+read_verilog ../top.v
+synth_ecp5 -top top
+write_verilog synth.v 

architecture/scripts/synth_ecp5_vpr.ys

+read_verilog ../top.v
+synth_ecp5 -vpr
+write_verilog synth.v 

architecture/scripts/synth_gowin.ys

+read_verilog ../top.v
+synth_gowin
+write_verilog synth.v 

architecture/scripts/synth_gowin_retime.ys

+read_verilog ../top.v
+synth_gowin -retime
+write_verilog synth.v 

architecture/scripts/synth_gowin_run.ys

+read_verilog ../top.v
+synth_gowin -run begin:vout
+write_verilog synth.v 

architecture/scripts/synth_gowin_top.ys

+read_verilog ../top.v
+synth_gowin -top top
+write_verilog synth.v 

architecture/scripts/synth_gowin_vout.ys

+read_verilog ../top.v
+synth_gowin -vout vout.v
+write_verilog synth.v 

architecture/scripts/synth_greenpak4.ys

+read_verilog ../top.v
+synth_greenpak4
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_json.ys

+read_verilog ../top.v
+synth_greenpak4 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_noflatten.ys

+read_verilog ../top.v
+synth_greenpak4 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_part140.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46140V
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_part620.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46620V
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_part621.ys

+read_verilog ../top.v
+synth_greenpak4 -part SLG46621V
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_retime.ys

+read_verilog ../top.v
+synth_greenpak4 -retime
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_run.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_greenpak4_top.ys

+read_verilog ../top.v
+synth_greenpak4 -top top
+write_verilog synth.v 

architecture/scripts/synth_ice40.ys

+read_verilog ../top.v
+synth_ice40
+write_verilog synth.v 

architecture/scripts/synth_ice40_abc2.ys

+read_verilog ../top.v
+synth_ice40 -abc2
+write_verilog synth.v 

architecture/scripts/synth_ice40_blif.ys

+read_verilog ../top.v
+synth_ice40 -blif blif.blif
+write_verilog synth.v 

architecture/scripts/synth_ice40_edif.ys

+read_verilog ../top.v
+synth_ice40 -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_ice40_flatten.ys

+read_verilog ../top.v
+synth_ice40 -flatten
+write_verilog synth.v 

architecture/scripts/synth_ice40_json.ys

+read_verilog ../top.v
+synth_ice40 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_ice40_nobram.ys

+read_verilog ../top.v
+synth_ice40 -nobram
+write_verilog synth.v 

architecture/scripts/synth_ice40_nocarry.ys

+read_verilog ../top.v
+synth_ice40 -nocarry
+write_verilog synth.v 

architecture/scripts/synth_ice40_nodffe.ys

+read_verilog ../top.v
+synth_ice40 -nodffe
+write_verilog synth.v 

architecture/scripts/synth_ice40_noflatten.ys

+read_verilog ../top.v
+synth_ice40 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_ice40_retime.ys

+read_verilog ../top.v
+synth_ice40 -retime
+write_verilog synth.v 

architecture/scripts/synth_ice40_run.ys

+read_verilog ../top.v
+synth_ice40 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_ice40_top.ys

+read_verilog ../top.v
+synth_ice40 -top top
+write_verilog synth.v 

architecture/scripts/synth_ice40_vpr.ys

+read_verilog ../top.v
+synth_ice40 -vpr
+write_verilog synth.v 

architecture/scripts/synth_intel.ys

+read_verilog ../top.v
+synth_intel
+write_verilog synth.v 

architecture/scripts/synth_intel_a10gx.ys

+read_verilog ../top.v
+synth_intel -family a10gx
+write_verilog synth.v 

architecture/scripts/synth_intel_cyclone10.ys

+read_verilog ../top.v
+synth_intel -family cyclone10
+write_verilog synth.v 

architecture/scripts/synth_intel_cycloneiv.ys

+read_verilog ../top.v
+synth_intel -family cycloneiv
+write_verilog synth.v 

architecture/scripts/synth_intel_cycloneive.ys

+read_verilog ../top.v
+synth_intel -family cycloneive
+write_verilog synth.v 

architecture/scripts/synth_intel_cyclonev.ys

+read_verilog ../top.v
+synth_intel -family cyclonev
+write_verilog synth.v 

architecture/scripts/synth_intel_max10.ys

+read_verilog ../top.v
+synth_intel -family max10
+write_verilog synth.v 

architecture/scripts/synth_intel_nobram.ys

+read_verilog ../top.v
+synth_intel -nobram
+write_verilog synth.v 

architecture/scripts/synth_intel_noflatten.ys

+read_verilog ../top.v
+synth_intel -flatten
+write_verilog synth.v 

architecture/scripts/synth_intel_noiopads.ys

+read_verilog ../top.v
+synth_intel -noiopads
+write_verilog synth.v 

architecture/scripts/synth_intel_retime.ys

+read_verilog ../top.v
+synth_intel -retime
+write_verilog synth.v 

architecture/scripts/synth_intel_run.ys

+read_verilog ../top.v
+synth_intel -run family:vpr
+write_verilog synth.v 

architecture/scripts/synth_intel_top.ys

+read_verilog ../top.v
+synth_intel -top top
+write_verilog synth.v 

architecture/scripts/synth_intel_vpr.ys

+read_verilog ../top.v
+synth_intel -vpr vpr.vpr
+write_verilog synth.v 

architecture/scripts/synth_intel_vqm.ys

+read_verilog ../top.v
+synth_intel -vqm vqm.vqm
+write_verilog synth.v 

architecture/scripts/synth_sf2.ys

+read_verilog ../top.v
+synth_sf2
+write_verilog synth.v 

architecture/scripts/synth_sf2_edif.ys

+read_verilog ../top.v
+synth_sf2 -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_sf2_json.ys

+read_verilog ../top.v
+synth_sf2 -json json.json
+write_verilog synth.v 

architecture/scripts/synth_sf2_noflatten.ys

+read_verilog ../top.v
+synth_sf2 -noflatten
+write_verilog synth.v 

architecture/scripts/synth_sf2_retime.ys

+read_verilog ../top.v
+synth_sf2 -retime
+write_verilog synth.v 

architecture/scripts/synth_sf2_run.ys

+read_verilog ../top.v
+synth_sf2 -run begin:json
+write_verilog synth.v 

architecture/scripts/synth_sf2_top.ys

+read_verilog ../top.v
+synth_sf2 -top top
+write_verilog synth.v 

architecture/scripts/synth_xilinx.ys

+read_verilog ../top.v
+synth_xilinx
+write_verilog synth.v 

architecture/scripts/synth_xilinx_blif.ys

+read_verilog ../top.v
+synth_xilinx -blif blif.blif
+write_verilog synth.v 

architecture/scripts/synth_xilinx_edif.ys

+read_verilog ../top.v
+synth_xilinx -edif edif.edif
+write_verilog synth.v 

architecture/scripts/synth_xilinx_flatten.ys

+read_verilog ../top.v
+synth_xilinx -flatten
+write_verilog synth.v 

architecture/scripts/synth_xilinx_retime.ys

+read_verilog ../top.v
+synth_xilinx -retime
+write_verilog synth.v 

architecture/scripts/synth_xilinx_run.ys

+read_verilog ../top.v
+synth_xilinx -run begin:blif
+write_verilog synth.v 

architecture/scripts/synth_xilinx_top.ys

+read_verilog ../top.v
+synth_xilinx -top top
+write_verilog synth.v 

architecture/scripts/synth_xilinx_vpr.ys

+read_verilog ../top.v
+synth_xilinx -vpr
+write_verilog synth.v 

architecture/synth_achronix/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_achronix/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_coolrunner2/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_coolrunner2/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_easic/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_easic/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_ecp5/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_ecp5/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_gowin/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_gowin/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_greenpak4/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_greenpak4/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_ice40/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_ice40/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_intel/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_intel_a10gx/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel_a10gx/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_intel_cyclone10/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel_cyclone10/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_intel_cycloneiv/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel_cycloneiv/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_intel_cycloneive/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel_cycloneive/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_intel_cyclonev/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel_cyclonev/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_sf2/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_sf2/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_xilinx/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_xilinx/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

backends/.gitignore

+/.stamp

backends/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+$(foreach design,$(1),
+$(foreach script,$(2),
+work:: $(design)/work_$(script)/.stamp
+
+$(design)/work_$(script)/.stamp:
+	bash run.sh $(design) $(script)
+
+clean::
+	rm -rf $(design)/work_$(script)
+))
+endef
+
+#write_aiger
+$(eval $(call template,write_aiger,write_aiger write_aiger_ascii write_aiger_zinit write_aiger_miter write_aiger_symbols write_aiger_map write_aiger_vmap write_aiger_I write_aiger_O write_aiger_B ))
+
+#write_blif
+$(eval $(call template,write_blif,write_blif write_blif_top write_blif_buf write_blif_unbuf write_blif_true  write_blif_false  write_blif_undef  write_blif_noalias  write_blif_icells  write_blif_gates  write_blif_conn  write_blif_attr  write_blif_param  write_blif_cname  write_blif_iname  write_blif_iattr  write_blif_blackbox  write_blif_impltf))
+
+#write_btor
+$(eval $(call template,write_btor,write_btor write_btor write_btor_v write_btor_s))
+$(eval $(call template,write_btor_logic,write_btor write_btor_v write_btor_s))
+$(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor_mem_s))
+$(eval $(call template,write_btor_pmux,write_btor_pmux))
+$(eval $(call template,write_btor_and_or,write_btor_and_or))
+
+#write_edif
+$(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
+
+#write_firrtl
+$(eval $(call template,write_firrtl,write_firrtl ))
+#ERROR: Unclocked write port 0 on memory top.ram.
+#$(eval $(call template,write_firrtl_mem,write_firrtl_mem ))
+
+#write_ilang
+$(eval $(call template,write_ilang,write_ilang write_ilang_selected))
+$(eval $(call template,write_ilang_mem,write_ilang write_ilang_selected))
+$(eval $(call template,write_ilang_mux,write_ilang write_ilang_selected))
+$(eval $(call template,write_ilang_fsm,write_ilang write_ilang_selected))
+$(eval $(call template,write_ilang_tri,write_ilang write_ilang_selected))
+
+#write_intersynth
+$(eval $(call template,write_intersynth,write_intersynth write_intersynth_selected write_intersynth_lib write_intersynth_notypes))
+
+#write_json
+$(eval $(call template,write_json,write_json write_json_aig))
+
+#write_simplec
+$(eval $(call template,write_simplec,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
+$(eval $(call template,write_simplec_mux,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
+$(eval $(call template,write_simplec_logic,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
+
+#write_smt2
+$(eval $(call template,write_smt2,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
+$(eval $(call template,write_smt2_logic,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
+$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
+$(eval $(call template,write_smt2_fsm,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
+$(eval $(call template,write_smt2_init_assert,write_smt2_init_assert))
+$(eval $(call template,write_smt2_reduce,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
+
+#write_smv
+$(eval $(call template,write_smv,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
+$(eval $(call template,write_smv_fsm,write_smv write_smv_noproc write_smv_verbose write_smv_tpl))
+$(eval $(call template,write_smv_reduce,write_smv_noproc))
+$(eval $(call template,write_smv_logic,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
+$(eval $(call template,write_smv_init_assert,write_smv_init_assert))
+$(eval $(call template,write_smv_cmos4,write_smv_cmos4))
+
+#write_spice
+$(eval $(call template,write_spice,write_spice write_spice_top write_spice_big_endian write_spice_neg_i write_spice_pos_i write_spice_nc_prefix write_spice_inames ))
+
+
+
+.PHONY: all clean

backends/common.v

+module assert_dff(input clk, input test, input pat);
+    always @(posedge clk)
+    begin
+        if (test != pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time);
+            $stop;
+        end
+    end
+endmodule 
+
+module assert_tri(input en, input A, input B);
+    always @(posedge en)
+    begin
+        #1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_Z(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A === 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_comb(input A, input B);
+    always @(*)
+    begin
+        #1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule

backends/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+sed -i 's/reg =/dummy =/' ./synth.v
+iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
+
+if ! vvp -N testbench > testbench.log 2>&1; then
+	grep 'ERROR' testbench.log
+	echo fail > ${1}_${2}.status
+elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

backends/scripts/write_aiger.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_B.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -B aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_I.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -I aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_O.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -O aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_ascii.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -ascii aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_map.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -map a.map aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_miter.ys

+read_verilog -sv ../top_clean.v
+synth -top top
+aigmap
+write_aiger -miter aiger.aiger
+write_verilog synth.v 

backends/scripts/write_aiger_symbols.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -symbols aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_vmap.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -vmap a.map aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_aiger_zinit.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -zinit aiger.aiger
+synth -top top
+write_verilog synth.v 

backends/scripts/write_blif.ys

+read_verilog -sv ../top.v
+proc
+write_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+proc
+opt
+write_blif blif2.blif
+design -reset
+read_verilog -sv ../top.v
+synth
+abc -lut 2
+write_blif blif3.blif
+design -reset
+read_verilog -sv ../top.v
+synth
+abc -sop
+write_blif blif4.blif
+design -reset
+read_verilog -sv ../top.v
+synth
+abc -g AND,XOR,NOR
+write_blif blif4.blif
+design -reset
+read_verilog -sv ../top.v
+synth
+abc -g ANDNOT,ORNOT
+write_blif blif4.blif
+design -reset
+read_verilog -sv ../top.v
+synth
+abc -g cmos3
+write_blif blif4.blif
+design -reset
+read_verilog -sv ../top.v
+abc -g AOI4
+synth -top top
+write_blif blif4.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v 

backends/scripts/write_blif_attr.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -attr blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_blackbox.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -blackbox blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_buf.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -buf a a a blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_cname.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -cname blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_conn.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -conn blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_false.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -false a a blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_gates.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -gates blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_iattr.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -iattr blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_icells.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -icells blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_impltf.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -impltf blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_iname.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -iname blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_noalias.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -noalias blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_param.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -param blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_top.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -top top blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_true.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -true a a blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_unbuf.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -unbuf a a a blif.blif
+write_verilog synth.v 

backends/scripts/write_blif_undef.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -undef a a blif.blif
+write_verilog synth.v 

backends/scripts/write_btor.ys

+read_verilog -sv ../top.v
+synth -top top
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+proc_init
+proc_mux
+proc_dff
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+synth
+abc
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+abc -g AND,XOR,NOR
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+abc -g ANDNOT,ORNOT
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+abc -g cmos3
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+abc -g AOI4
+synth -top top
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+abc -g OAI4
+synth -top top
+write_btor btor.btor
+design -reset
+read_verilog -sv ../top.v
+aigmap
+synth -top top
+write_btor btor.btor
+design -reset
+read_verilog  -sv ../top_clean.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_and_or.ys

+read_verilog -sv ../top.v
+proc
+write_btor btor.btor
+design -reset
+read_verilog  -sv ../top.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_logic_and.ys

+read_verilog -sv ../top.v
+memory_collect
+proc
+write_btor btor.btor
+design -reset
+read_verilog  -sv ../top.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_mem.ys

+read_verilog -sv ../top.v
+memory_collect
+proc
+write_btor btor.btor
+design -reset
+read_verilog  -sv ../top.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_mem_s.ys

+read_verilog -sv ../top.v
+memory_collect
+proc
+write_btor -s btor.btor
+design -reset
+read_verilog  -sv ../top.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_mem_v.ys

+read_verilog -sv ../top.v
+memory_collect
+proc
+write_btor -v btor.btor
+design -reset
+read_verilog  -sv ../top.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_pmux.ys

+read_verilog -sv ../top.v
+proc
+write_btor -v btor.btor
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_s.ys

+read_verilog -sv ../top.v
+synth -top top
+write_btor -s btor.btor
+design -reset
+read_verilog  -sv ../top_clean.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_simplemap.ys

+read_verilog -sv ../top.v
+synth -top top
+simplemap
+write_btor btor.btor
+design -reset
+read_verilog  -sv ../top_clean.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_btor_v.ys

+read_verilog -sv ../top.v
+synth -top top
+write_btor -v btor.btor
+design -reset
+read_verilog  -sv ../top_clean.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_edif.ys

+read_verilog ../top.v
+proc
+write_edif edif.edif
+write_verilog synth.v 

backends/scripts/write_edif_attrprop.ys

+read_verilog ../top.v
+proc
+write_edif -attrprop edif.edif
+write_verilog synth.v 

backends/scripts/write_edif_nogndvcc.ys

+read_verilog ../top.v
+proc
+write_edif -nogndvcc edif.edif
+write_verilog synth.v 

backends/scripts/write_edif_pvector_ang.ys

+read_verilog ../top.v
+proc
+write_edif -pvector ang edif.edif
+write_verilog synth.v 

backends/scripts/write_edif_pvector_bra.ys

+read_verilog ../top.v
+proc
+write_edif -pvector bra edif.edif
+write_verilog synth.v 

backends/scripts/write_edif_pvector_par.ys

+read_verilog ../top.v
+proc
+write_edif -pvector par edif.edif
+write_verilog synth.v 

backends/scripts/write_edif_top.ys

+read_verilog ../top.v
+proc
+write_edif -top top edif.edif
+write_verilog synth.v 

backends/scripts/write_firrtl.ys

+read_verilog ../top.v
+proc
+write_firrtl firrtl.firrtl
+write_verilog synth.v 

backends/scripts/write_firrtl_mem.ys

+read_verilog ../top.v
+memory_collect
+proc
+write_firrtl firrtl.firrtl
+write_verilog synth.v 

backends/scripts/write_ilang.ys

+read_verilog ../top.v
+proc
+dump -o file.il
+write_ilang ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v 

backends/scripts/write_ilang_selected.ys

+read_verilog ../top.v
+proc
+dump -a file.il
+write_ilang -selected ilang.ilang
+dump -m -a file1.il
+write_verilog synth.v 

backends/scripts/write_intersynth.ys

+read_verilog ../top.v
+proc
+write_intersynth intersynth.intersynth
+write_verilog synth.v 

backends/scripts/write_intersynth_lib.ys

+read_verilog ../top.v
+proc
+write_intersynth -lib ../top.v intersynth.intersynth
+write_verilog synth.v 

backends/scripts/write_intersynth_notypes.ys

+read_verilog ../top.v
+proc
+write_intersynth -notypes intersynth.intersynth
+write_verilog synth.v 

backends/scripts/write_intersynth_selected.ys

+read_verilog ../top.v
+proc
+write_intersynth -selected intersynth.intersynth
+write_verilog synth.v 

backends/scripts/write_json.ys

+read_verilog ../top.v
+proc
+write_json json.json
+write_verilog synth.v 

backends/scripts/write_json_aig.ys

+read_verilog ../top.v
+proc
+write_json -aig json.json
+write_verilog synth.v 

backends/scripts/write_simplec.ys

+read_verilog ../top.v
+synth -top top
+write_simplec c.c
+write_verilog synth.v 

backends/scripts/write_simplec_cmos3.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos3
+write_simplec c.c
+write_verilog synth.v 

backends/scripts/write_simplec_cmos4.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos4
+write_simplec c.c
+write_verilog synth.v 

backends/scripts/write_simplec_i16.ys

+read_verilog ../top.v
+synth -top top
+write_simplec -i16 c.c
+write_verilog synth.v 

backends/scripts/write_simplec_i32.ys

+read_verilog ../top.v
+synth -top top
+write_simplec -i32 c.c
+write_verilog synth.v 

backends/scripts/write_simplec_i64.ys

+read_verilog ../top.v
+synth -top top
+write_simplec -i64 c.c
+write_verilog synth.v 

backends/scripts/write_simplec_i8.ys

+read_verilog ../top.v
+synth -top top
+write_simplec -i8 c.c
+write_verilog synth.v 

backends/scripts/write_simplec_verbose.ys

+read_verilog ../top.v
+synth -top top
+write_simplec -verbose c.c
+write_verilog synth.v 

backends/scripts/write_smt2.ys

+read_verilog ../top.v
+proc
+write_smt2 smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_bv.ys

+read_verilog ../top.v
+proc
+write_smt2 -bv smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_init_assert.ys

+read_verilog -sv ../top.v
+proc
+write_smt2 smt2.smt2
+synth -top top
+write_smt2 smt2.smt2
+design -reset
+read_verilog  -sv ../top_clean.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_smt2_mem.ys

+read_verilog ../top.v
+proc
+write_smt2 -mem smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_mem_memtest.ys

+read_verilog ../top.v
+memory_collect
+proc
+write_smt2 -mem smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_memtest.ys

+read_verilog ../top.v
+memory_collect
+proc
+write_smt2 smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_nobv.ys

+read_verilog ../top.v
+synth
+write_smt2 -nobv smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_nomem.ys

+read_verilog ../top.v
+proc
+write_smt2 -nomem smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_stbv.ys

+read_verilog ../top.v
+proc
+write_smt2 -stbv smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_stbv_memtest.ys

+read_verilog ../top.v
+memory_collect
+proc
+write_smt2 -stbv smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_stdt.ys

+read_verilog ../top.v
+proc
+write_smt2 -stdt smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_synth.ys

+read_verilog ../top.v
+synth -top top
+write_smt2 smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_tpl.ys

+read_verilog ../top.v
+proc
+write_smt2 -tpl ../top.tpl smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_verbose.ys

+read_verilog ../top.v
+proc
+write_smt2 -verbose smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smt2_wires.ys

+read_verilog ../top.v
+proc
+write_smt2 -wires smt2.smt2
+write_verilog synth.v 

backends/scripts/write_smv.ys

+read_verilog ../top.v
+proc
+write_smv smv.smv
+write_verilog synth.v 

backends/scripts/write_smv_cmos4.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos4
+write_smv smv.smv
+write_verilog synth.v 

backends/scripts/write_smv_init_assert.ys

+read_verilog -sv ../top.v
+synth -top top
+write_smv smv.smv
+design -reset
+read_verilog  -sv ../top_clean.v
+synth -top top
+write_verilog synth.v 

backends/scripts/write_smv_noproc.ys

+read_verilog ../top.v
+write_smv smv.smv
+synth -top top
+write_verilog synth.v 

backends/scripts/write_smv_synth.ys

+read_verilog ../top.v
+synth -top top
+write_smv smv.smv
+write_verilog synth.v 

backends/scripts/write_smv_tpl.ys

+read_verilog ../top.v
+proc
+write_smv -tpl ../top.tpl smv.smv
+write_verilog synth.v 

backends/scripts/write_smv_verbose.ys

+read_verilog ../top.v
+proc
+write_smv -verbose smv.smv
+write_verilog synth.v 

backends/scripts/write_spice.ys

+read_verilog ../top.v
+proc
+write_spice sp.sp
+write_verilog synth.v 

backends/scripts/write_spice_big_endian.ys

+read_verilog ../top.v
+proc
+write_spice -big_endian sp.sp
+write_verilog synth.v 

backends/scripts/write_spice_inames.ys

+read_verilog ../top.v
+proc
+write_spice -inames sp.sp
+write_verilog synth.v 

backends/scripts/write_spice_nc_prefix.ys

+read_verilog ../top.v
+proc
+write_spice -nc_prefix sp.sp
+write_verilog synth.v 

backends/scripts/write_spice_neg_i.ys

+read_verilog ../top.v
+proc
+write_spice -neg i sp.sp
+write_verilog synth.v 

backends/scripts/write_spice_pos_i.ys

+read_verilog ../top.v
+proc
+write_spice -pos i sp.sp
+write_verilog synth.v 

backends/scripts/write_spice_top.ys

+read_verilog ../top.v
+proc
+write_spice -top top sp.sp
+write_verilog synth.v 

backends/write_aiger/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_aiger/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+ 
+
+ 
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate) 
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);    
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate) 
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_aiger/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_blif/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

backends/write_blif/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ reg A1,cout1;
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(negedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(*) begin
+    if (x)
+        A <=  A1|y~&cin;
+end
+always @(*) begin
+    if (~x)
+        cout <=  cout1&cin~|y;
+end
+`else
+assign {cout,A} =  1'bZ;
+`endif
+
+bb ubb (cin,y,x,A);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+
+ output reg out1;
+endmodule

backends/write_btor/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_btor/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output reg B,C
+ );
+ 
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+ 
+ 
+
+ 
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate) 
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);    
+    assume(s_eventually too);
+end
+always @(posedge x) begin
+    if ($initstate) 
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+assign {B,C} =  {cout,A} <<< 1;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_btor/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_btor_and_or/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_btor_and_or/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

backends/write_btor_logic/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

backends/write_btor_logic/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ reg A1,cout1;
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+`else
+assign {cout,A} =  1'bZ;
+`endif
+
+endmodule

backends/write_btor_logic/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_btor_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clk(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_btor_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_btor_pmux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    reg [1:0] S = 0;
+    wire [3:0] Y;
+
+    top uut (
+        .C (clk),
+        .S (S ),
+        .Y (Y )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+    S <= S + 1;
+    end
+	
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(Y[0]|Y[1]|Y[2]|Y[3]));
+  
+endmodule

backends/write_btor_pmux/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

backends/write_edif/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_edif/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+bb ubb (cin,y,x);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk);
+ input in1;
+ input in2;
+ input clk;
+endmodule

backends/write_firrtl/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_firrtl/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

backends/write_firrtl_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clka(clk),
+	.clkb(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_firrtl_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_ilang/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_ilang/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

backends/write_ilang_fsm/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_ilang_fsm/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

backends/write_ilang_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clka(clk),
+	.clkb(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_ilang_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_ilang_mux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

backends/write_ilang_mux/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG 
+    
+    always @(*)
+		Y = (S)? B : A;
+`else
+	
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG 
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG 
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y); 
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+	
+assign Y = D[S];
+ 
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+    
+    
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+    
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+    
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

backends/write_ilang_tri/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_ilang_tri/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

backends/write_intersynth/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_intersynth/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_json/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_json/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_simplec/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_simplec/top.v

+module tristate (en, i, o);
+    input en;
+    input i;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG  
+    assign	io[0] = i & ~en;
+    assign	io[1] = i ? en : ~en;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_simplec_logic/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	wire patt_B;
+	wire B;
+	wire x,y,z,A;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+    assign  patt_B = (x || y || !z)?  (A & z) : ~x;
+    assign x = in[1:2];
+    assign y = in[3:4];
+    assign z = in[5:6];
+    assign A = in[7];
+
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_simplec_logic/top.v

+module top
+(
+ input x,
+ input y,
+ input z,
+ input clk,
+
+ input A,
+ output B
+ );
+ 
+`ifndef BUG
+assign  B = (x || y || !z)?  (A & z) : ~x;
+`else
+assign B =  z - y + x;
+
+`endif
+
+endmodule

backends/write_simplec_mux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

backends/write_simplec_mux/top.v

+module mux16 (D, S, Y); 
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+`ifndef BUG	
+assign Y = D[S];
+`else
+assign Y = D[S+1];
+`endif 
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M16
+);
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

backends/write_smt2/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_smt2/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smt2/top.v

+module tristate (en, i, o);
+    input en;
+    input i;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smt2_fsm/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_smt2_fsm/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smt2_fsm/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+
+	//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

backends/write_smt2_init_assert/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_smt2_init_assert/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smt2_init_assert/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output reg B,C
+ );
+ 
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+ 
+ 
+
+ 
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate) 
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);    
+    assume(s_eventually too);
+end
+always @(posedge x) begin
+    if ($initstate) 
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+assign {B,C} =  {cout,A} << 1;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_smt2_init_assert/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_smt2_logic/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	wire patt_B;
+	wire B;
+	wire x,y,z,A;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+    assign  patt_B = (x || y || !z)?  (A & z) : ~x;
+    assign x = in[1:2];
+    assign y = in[3:4];
+    assign z = in[5:6];
+    assign A = in[7];
+
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_smt2_logic/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smt2_logic/top.v

+module top
+(
+ input x,
+ input y,
+ input z,
+ input clk,
+
+ input A,
+ output B
+ );
+ 
+`ifndef BUG
+assign  B = (x || y || !z)?  (A & z) : ~x;
+`else
+assign B =  z - y + x;
+
+`endif
+
+endmodule

backends/write_smt2_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clka(clk),
+	.clkb(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_smt2_mem/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smt2_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_smt2_nobv/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA;
+    wire [1:0] dinB;    
+    wire [1:0] dinC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dinB ),
+        .c (dinC )
+    );
+    
+    initial begin
+        dinA <= 1;
+        #10
+        dinA <= 0;
+        #10
+        dinA <= 1;
+    end
+    
+endmodule

backends/write_smt2_nobv/top.v

+module tristate (en, i, o);
+    input en;
+    input i;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+
+    assign	io[0] = i & ~en;
+    assign	io[1] = i ? en : ~en;
+		
+    assign o = io;
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smt2_reduce/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

backends/write_smt2_reduce/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smt2_reduce/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ reg A1,cout1;
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+`else
+assign {cout,A} =  1'bZ;
+`endif
+
+endmodule

backends/write_smv/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_smv/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smv/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

backends/write_smv_cmos4/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	wire patt_B;
+	wire B;
+	wire x,y,z,A;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+    assign  patt_B = (x || y || !z)?  (A & z) : ~x;
+    assign x = in[1:2];
+    assign y = in[3:4];
+    assign z = in[5:6];
+    assign A = in[7];
+
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_smv_cmos4/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smv_cmos4/top.v

+module top
+(
+ input x,
+ input y,
+ input z,
+ input clk,
+
+ input A,
+ output signed B,
+ output signed C,D,E
+ );
+ 
+`ifndef BUG
+assign  B = (x || y || !z)?  (A & z) : ~x;
+assign {D,C} =  {y,z} >>> 1;
+assign E = {x,y,z} / 3;
+`else
+assign B =  z - y + x;
+
+`endif
+
+endmodule

backends/write_smv_fsm/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

backends/write_smv_fsm/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smv_fsm/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+
+	//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

backends/write_smv_init_assert/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_smv_init_assert/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smv_init_assert/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output reg B,C
+ );
+ 
+ reg ASSERT = 1;
+ 
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+assign    A =  y + cin;
+assign    cout =  y + A;
+    always @*
+    assert(ASSERT);
+assign {B,C} =  {cout,A} <<< 1;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_smv_init_assert/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_smv_logic/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	wire patt_B;
+	wire B;
+	wire x,y,z,A;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+    assign  patt_B = (x || y || !z)?  (A & z) : ~x;
+    assign x = in[1:2];
+    assign y = in[3:4];
+    assign z = in[5:6];
+    assign A = in[7];
+
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_smv_logic/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smv_logic/top.v

+module top
+(
+ input x,
+ input y,
+ input z,
+ input clk,
+
+ input A,
+ output signed B,
+ output signed C,D,E
+ );
+ 
+`ifndef BUG
+assign  B = (x || y || !z)?  (A & z) : ~x;
+assign {D,C} =  {y,z} >>> 1;
+assign E = {x,y,z} / 3;
+`else
+assign B =  z - y + x;
+
+`endif
+
+endmodule

backends/write_smv_reduce/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

backends/write_smv_reduce/top.tpl

+; we need QF_UFBV for this poof
+        (set-logic QF_UFBV)
+
+        ; insert the auto-generated code here
+        %%
+
+        ; declare two state variables s1 and s2
+        (declare-fun s1 () test_s)
+        (declare-fun s2 () test_s)
+
+        ; state s2 is the successor of state s1
+        (assert (test_t s1 s2))
+
+        ; we are looking for a model with y non-zero in s1
+        (assert (distinct (|test_n y| s1) #b0000))
+
+        ; we are looking for a model with y zero in s2
+        (assert (= (|test_n y| s2) #b0000))
+
+        ; is there such a model?
+        (check-sat)
+ 

backends/write_smv_reduce/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+ 
+ wire A1,cout1;
+ 
+//  initial begin
+//     A = 0;
+//     cout = 0;
+//  end
+
+`ifndef BUG
+assign A1 =  ~y + &cin;
+assign cout1 = cin ? |y : ^A;
+
+assign A =  A1|y~&cin~^A1;
+assign cout =  cout1&cin~|y;
+`else
+assign {cout,A} =  1'bZ;
+`endif
+
+endmodule

backends/write_spice/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_spice/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

frontends/.gitignore

+/alu/work_*/
+/.stamp

frontends/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+$(foreach design,$(1),
+$(foreach script,$(2),
+work:: $(design)/work_$(script)/.stamp
+
+$(design)/work_$(script)/.stamp:
+	bash run.sh $(design) $(script)
+
+clean::
+	rm -rf $(design)/work_$(script)
+))
+endef
+
+#read_blif
+$(eval $(call template,read_blif,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_and_or,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_fsm,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_logic,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_mem,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
+$(eval $(call template,read_blif_eblif,read_blif_eblif))
+
+#read_ilang
+$(eval $(call template,read_ilang,read_ilang read_ilang_selected))
+$(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected))
+$(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected))
+$(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected))
+$(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
+
+#read_json
+$(eval $(call template,read_json,read_json))
+$(eval $(call template,read_json_fsm,read_json))
+$(eval $(call template,read_json_logic,read_json))
+$(eval $(call template,read_json_mem,read_json))
+$(eval $(call template,read_json_mux,read_json))
+$(eval $(call template,read_json_tri,read_json))
+
+#read_liberty  read_liberty_lib
+$(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_arith,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_ff,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_ff_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_ff_np,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_ff_pn,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_ff_pp,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+.PHONY: all clean

frontends/common.v

+module assert_dff(input clk, input test, input pat);
+    always @(posedge clk)
+    begin
+        if (test != pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_tri(input en, input A, input B);
+    always @(posedge en)
+    begin
+        #1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_Z(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A === 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule
+
+module assert_comb(input A, input B);
+    always @(*)
+    begin
+        #1;
+        if (A !== B)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
+            $stop;
+        end
+    end
+endmodule

frontends/read_blif/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

frontends/read_blif/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

frontends/read_blif_and_or/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

frontends/read_blif_and_or/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

frontends/read_blif_eblif/eblif.eblif

+
+.model top
+.names a b
+.inputs a
+.outputs b
+.conn a b
+.names a b c
+11 1
+.cname $my_and_gate
+.latch a_and_b dff_q re clk 0
+.attr src my_design.v:42
+.end

frontends/read_blif_eblif/testbench.v

+module testbench;
+    reg a;
+
+	wire b = 1'bx;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 a = 0;
+        repeat (10000) begin
+            #5 a = ~a;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.a(a),
+	.b(b)
+	);
+
+	assert_comb b_test(.A(1'bx),.B(b));
+
+endmodule

frontends/read_blif_fsm/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

frontends/read_blif_fsm/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

frontends/read_blif_logic/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

frontends/read_blif_logic/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ reg A1,cout1;
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+`else
+assign {cout,A} =  1'bZ;
+`endif
+
+endmodule

frontends/read_blif_logic/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

frontends/read_blif_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clk(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

frontends/read_blif_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	parameter WIDTH=8;
+	// Declare the RAM variable
+	reg [WIDTH-1:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

frontends/read_blif_mux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/read_blif_mux/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+parameter dw=4;
+
+input[1:0] S;
+input[dw-1:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[dw-1:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 #(4) u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/read_blif_pmux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    reg [1:0] S = 0;
+    wire [3:0] Y;
+
+    top uut (
+        .C (clk),
+        .S (S ),
+        .Y (Y )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+    S <= S + 1;
+    end
+	
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(Y[0]|Y[1]|Y[2]|Y[3]));
+  
+endmodule

frontends/read_blif_pmux/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

frontends/read_blif_tri/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

frontends/read_blif_tri/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

frontends/read_ilang/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

frontends/read_ilang/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

frontends/read_ilang_fsm/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

frontends/read_ilang_fsm/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

frontends/read_ilang_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clka(clk),
+	.clkb(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

frontends/read_ilang_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

frontends/read_ilang_mux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/read_ilang_mux/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG 
+    
+    always @(*)
+		Y = (S)? B : A;
+`else
+	
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG 
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG 
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y); 
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+	
+assign Y = D[S];
+ 
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+    
+    
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+    
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+    
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/read_ilang_tri/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

frontends/read_ilang_tri/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

frontends/read_json/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

frontends/read_json/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

frontends/read_json_fsm/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

frontends/read_json_fsm/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

frontends/read_json_logic/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

frontends/read_json_logic/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

frontends/read_json_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clka(clk),
+	.clkb(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

frontends/read_json_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

frontends/read_json_mux/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/read_json_mux/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG 
+    
+    always @(*)
+		Y = (S)? B : A;
+`else
+	
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG 
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG 
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y); 
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+	
+assign Y = D[S];
+ 
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+    
+    
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+    
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+    
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/read_json_tri/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

frontends/read_json_tri/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

frontends/read_liberty/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty/testbench.v

+module testbench;
+    reg a;
+
+	wire b = 1'bx;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 a = 0;
+        repeat (10000) begin
+            #5 a = ~a;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.A(a),
+	.Y(b)
+	);
+
+	assert_comb b_test(.A(~a),.B(b));
+
+endmodule

frontends/read_liberty_arith/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+
+  cell(top) {
+    pin(regA) {
+	direction : output ;
+	capacitance : 0.001;
+	function : "(y | x & cin)";
+    }
+    pin(regcout) {
+	direction : inout ;
+	capacitance : 0.001;
+	function : "(y + x & cin ^ regA)";
+    }
+    pin(x) {
+	direction : input ;
+	max_transition : 2.5;
+	capacitance : 0.001;
+    }
+    pin(y) {
+	direction : input ;
+	max_transition : 2.5;
+	capacitance : 0.001;
+    }
+    pin(cin) {
+	direction : input ;
+	max_transition : 2.5;
+	capacitance : 0.001;
+    }
+  }
+}

frontends/read_liberty_arith/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.regA(out),
+	.regcout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

frontends/read_liberty_diff_inv/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+cell_footprint : inv;
+area : 129.6;
+cell_leakage_power : 0.0310651;
+pin(A) {
+direction : input;
+capacitance : 0.0159685;
+rise_capacitance : 0.0159573;
+fall_capacitance : 0.0159685; }
+pin(Y) {
+direction : output;
+capacitance : 0;
+rise_capacitance : 0;
+fall_capacitance : 0;
+max_capacitance : 0.394734;
+function : "(!A)";
+timing() {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise(delay_template_5x5) {
+index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
+index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
+values ( \
+"0.147955, 0.218038, 0.359898, 0.922746, 1.76604", \
+"0.224384, 0.292903, 0.430394, 0.991288, 1.83116", \
+"0.365378, 0.448722, 0.584275, 1.13597, 1.97017", \
+"0.462096, 0.551586, 0.70164, 1.24437, 2.08131", \
+"0.756459, 0.874246, 1.05713, 1.62898, 2.44989"); }
+rise_transition(delay_template_5x5) {
+index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
+index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
+values ( ... ); }
+cell_fall(delay_template_5x5) {
+index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
+index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
+values ( ... ); }
+fall_transition(delay_template_5x5) {
+index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
+index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
+values ( ... ); }
+} /* end timing */
+internal_power() {
+related_pin : "A";
+rise_power(energy_template_5x5) {
+index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
+index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
+values ( ... ); }
+fall_power(energy_template_5x5) {
+index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
+index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
+values ( ... ); }
+} /* end internal_power */
+} /* end Pin Y */
+} /* end INVX1 */
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_diff_inv/testbench.v

+module testbench;
+    reg a;
+
+	wire b = 1'bx;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 a = 0;
+        repeat (10000) begin
+            #5 a = ~a;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.A(a),
+	.Y(b)
+	);
+
+	assert_comb b_test(.A(~a),.B(b));
+
+endmodule

frontends/read_liberty_ff/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+next_state : " D ";
+clocked_on : " CLK ";
+clear : " CLR ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_ff/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_ff_n/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+next_state : " D ";
+clocked_on : " CLK ";
+clear : " CLR ";
+preset : " PRE ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( PRE ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin PRE */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+timing () { /* propagation delay from falling edge of preset to Q=1 */
+timing_type : preset;
+timing_sense : negative_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "PRE";
+} /* end of Q timing related to PRE */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_ff_n/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_ff_np/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+next_state : " D ";
+clocked_on : " CLK ";
+clear : " CLR ";
+preset : " PRE ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( PRE ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin PRE */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : negative_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+timing () { /* propagation delay from falling edge of preset to Q=1 */
+timing_type : preset;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "PRE";
+} /* end of Q timing related to PRE */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_ff_np/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_ff_pn/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+next_state : " D ";
+clocked_on : " CLK ";
+clear : " CLR ";
+preset : " PRE ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( PRE ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin PRE */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+timing () { /* propagation delay from falling edge of preset to Q=1 */
+timing_type : preset;
+timing_sense : negative_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "PRE";
+} /* end of Q timing related to PRE */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_ff_pn/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_ff_pp/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+next_state : " D ";
+clocked_on : " CLK ";
+clear : " CLR ";
+preset : " PRE ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( PRE ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin PRE */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+timing () { /* propagation delay from falling edge of preset to Q=1 */
+timing_type : preset;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "PRE";
+} /* end of Q timing related to PRE */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_ff_pp/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_latch/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "latch";
+latch(IQ, IQN) {
+enable : "CLK" ;
+data_in : "D" ;
+clear : "CLR" ;}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_latch/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_latch_n/lib.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "latch";
+latch(IQ, IQN) {
+enable : "CLK" ;
+data_in : "D" ;
+preset : "CLR" ;}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_falling;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_falling;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : falling_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : preset;
+timing_sense : negative_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_latch_n/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	wire out = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.CLK(in[0]),
+	.D(in[1]),
+	.CLR(in[2]),
+	.Q(out)
+	);
+
+
+
+   always @(posedge in[0] or posedge in[2])
+    if (in[2])
+      patt_out <= 0;
+    else
+      patt_out <= in[1];
+
+	assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
+
+endmodule

frontends/read_liberty_tri/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+/* Enabled inverter or tristate inverter */
+cell(top) {
+area : 324;
+cell_footprint : "eninv";
+pin(A) {
+direction : input;
+capacitance : 0.027;
+} /* end of pin A */
+pin(En) {
+direction : input;
+capacitance : 0.0135;
+} /*end of pin En */
+pin(Y) {
+direction : output;
+function : "A";
+three_state : "En";
+timing () {
+timing_sense : negative_unate;
+related_pin : "A";
+cell_rise(lu5x5) { values( " ... " );}
+rise_transition(lu5x5) { values( " ... " );}
+cell_fall(lu5x5) { values( " ... " );}
+fall_transition(lu5x5) { values( " ... " );}
+} /* end of enabled timing */
+timing() {
+timing_sense : positive_unate;
+timing_type : three_state_enable;
+related_pin : "En";
+cell_rise(delay_template_5x5) { values( " ... " );}
+rise_transition(delay_template_5x5) { values( " ... " );}
+cell_fall(delay_template_5x5) { values( " ... " );}
+fall_transition(delay_template_5x5) { values( " ... " );}
+} /* end of enable timing */
+timing() {
+timing_sense : negative_unate;
+timing_type : three_state_disable;
+related_pin : "En";
+cell_rise(delay_template_5x1) { values( " ... " );}
+rise_transition(delay_template_5x1) { values( " ... " );}
+cell_fall(delay_template_5x1) { values( " ... " );}
+fall_transition(delay_template_5x1) { values( " ... " );}
+} /* end of disable timing */
+} /* end of pin Y */
+} /* end of eninv */
+
+
+}

frontends/read_liberty_tri/testbench.v

+module testbench;
+    reg a;
+	reg En = 1'b1;
+	wire b = 1'bx;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 a = 0;
+        repeat (10000) begin
+            #5 a = ~a;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.A(a),
+	.En(En),
+	.Y(b)
+	);
+
+	assert_comb b_test(.A(a),.B(b));
+
+endmodule

frontends/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+sed -i 's/reg =/dummy =/' ./synth.v
+iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
+
+if ! vvp -N testbench > testbench.log 2>&1; then
+	grep 'ERROR' testbench.log
+	echo fail > ${1}_${2}.status
+elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

frontends/scripts/read_blif.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v 

frontends/scripts/read_blif_attr.ys

+read_verilog ../top.v
+synth -top top
+write_blif -attr blif1.blif
+design -reset
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_buf.ys

+read_verilog ../top.v
+synth -top top
+write_blif -buf a a a blif1.blif
+design -reset
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_cname.ys

+read_verilog ../top.v
+synth -top top
+write_blif -cname blif1.blif
+design -reset
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_conn.ys

+read_verilog ../top.v
+synth -top top
+write_blif -conn blif1.blif
+design -reset
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_eblif.ys

+read_blif -wideports ../eblif.eblif
+synth -top top
+write_verilog synth.v

frontends/scripts/read_blif_param.ys

+read_verilog ../top.v
+synth -top top
+write_blif -param blif1.blif
+design -reset
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_sop.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -sop blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v 

frontends/scripts/read_blif_wideports.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -wideports blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v 

frontends/scripts/read_ilang.ys

+read_verilog ../top.v
+proc
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v

frontends/scripts/read_ilang_selected.ys

+read_verilog ../top.v
+proc
+dump -o file.il
+write_ilang -selected ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v

frontends/scripts/read_json.ys

+read_verilog ../top.v
+write_json json.json
+design -reset
+read_json json.json
+write_verilog synth.v

frontends/scripts/read_liberty.ys

+read_liberty -lib ../lib.lib
+design -reset
+read_liberty ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_ignore_miss_data_latch.ys

+read_liberty -ignore_miss_data_latch ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_ignore_miss_dir.ys

+read_liberty -ignore_miss_dir ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_ignore_miss_func.ys

+read_liberty -ignore_miss_func ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_lib.ys

+read_liberty -lib ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_nooverwrite.ys

+read_liberty -nooverwrite ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_setattr.ys

+read_liberty -setattr a ../lib.lib
+synth -top top
+write_verilog synth.v

simple/memory/testbench.v

@@ -24,6 +24,7 @@ module testbench;
     reg re_a = 1;
 	reg re_b = 1;
 	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
 
     top uut (
     .data_a(data_a),
@@ -47,6 +48,12 @@ module testbench;
     addr_a <= addr_a + 1;	
     addr_b <= addr_b + 1;
     end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
 	
 	always @(posedge clk) begin
     //#3;
@@ -54,16 +61,16 @@ module testbench;
     we_b <= !we_b; 
     end
 	
-	uut_mem_checker port_a_test(.clk(clk), .en(!we_a), .A(q_a));
-    uut_mem_checker port_b_test(.clk(clk), .en(!we_b), .A(q_b));
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
     
 endmodule
 
-module uut_mem_checker(input clk, input en, input [7:0] A);
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
     always @(posedge clk)
     begin
         #1;
-        if (en == 1 & A === 8'bXXXXXXXX)
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
             $stop;