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lvzhengyang
yosys-tests
Commits
c9bbc986
Commit
c9bbc986
authored
Jul 02, 2019
by
Eddie Hung
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script -select -> script -scriptwire
parent
12b1e247
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architecture/synth_xilinx_srl/run-test.sh
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architecture/synth_xilinx_srl/run-test.sh
View file @
c9bbc986
...
...
@@ -29,7 +29,7 @@ ${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
synth_xilinx;
\
design -copy-from __test __test;
\
select -assert-any __test;
\
script -s
elect
__test/w:assert_area'
\
script -s
criptwire
__test/w:assert_area'
\
-l ../../../../../techlibs/xilinx/cells_sim.v"
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
test21
*
.v
EXTRA_FLAGS
=
"
\
-f 'verilog -noblackbox -icells'
\
...
...
@@ -37,5 +37,5 @@ ${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="\
synth_xilinx -retime;
\
design -copy-from __test __test;
\
select -assert-any __test;
\
script -s
elect
__test/w:assert_area'
\
script -s
criptwire
__test/w:assert_area'
\
-l ../../../../../techlibs/xilinx/cells_sim.v"
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