Merge pull request #28 from SergeyDegtyar/master

Fix failed tests for dffe cell

architecture/synth_anlogic/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
 

architecture/synth_anlogic/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG
 			q <= d;

architecture/synth_ecp5/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ecp5/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_greenpak4/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_greenpak4/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_ice40/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ice40/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_xilinx/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_xilinx/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/async2sync/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/async2sync/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/clk2fflogic/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/clk2fflogic/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/dff2dffe_unmap/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/dff2dffs/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
 

simple/extract/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
 

simple/flowmap/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/flowmap/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/hierarchy/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/hierarchy/top.v

@@ -47,7 +47,7 @@ module dffe
     initial begin
       q = Z;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/hierarchy_huge/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/hierarchy_huge/top.v

@@ -47,7 +47,7 @@ module dffe
     initial begin
       q = Z;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/prep/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/prep/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/synth/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/synth/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/uniquify/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/uniquify/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 1'bZ;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;