Merge pull request #28 from SergeyDegtyar/master

Fix failed tests for dffe cell

architecture/synth_anlogic/testbench.v

@@ -11,10 +11,10 @@ module testbench;
             #5 clk = 0;
         end
 
-        $display("OKAY");    
+        $display("OKAY");
     end
-   
-    
+
+
     reg [2:0] dinA = 0;
     wire doutB,doutB1,doutB2,doutB3,doutB4;
 	reg dff,ndff,adff,adffn,dffe = 0;
@@ -30,12 +30,12 @@ module testbench;
         .b3 (doutB3 ),
         .b4 (doutB4 )
     );
-    
+
     always @(posedge clk) begin
     #3;
     dinA <= dinA + 1;
     end
-	
+
 	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
 		if ( dinA[2] )
 			dff <= 1'b0;
@@ -43,7 +43,7 @@ module testbench;
 			dff <= 1'b1;
 		else
             dff <= dinA[0];
-    
+
     always @( negedge clk, negedge dinA[1], negedge dinA[2] )
 		if ( !dinA[2] )
 			ndff <= 1'b0;
@@ -51,27 +51,27 @@ module testbench;
 			ndff <= 1'b1;
 		else
             ndff <= dinA[0];
-            
+
     always @( posedge clk, posedge dinA[2] )
 		if ( dinA[2] )
 			adff <= 1'b0;
 		else
             adff <= dinA[0];
-            
+
     always @( posedge clk, negedge dinA[2] )
 		if ( !dinA[2] )
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
-            
+
 	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
     assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
-    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
     assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
     assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
-    
+
 endmodule

architecture/synth_anlogic/top.v

@@ -5,9 +5,9 @@ module adff
     end
 	always @( posedge clk, posedge clr )
 		if ( clr )
-`ifndef BUG        
+`ifndef BUG
 			q <= 1'b0;
-`else        
+`else
 			q <= d;
 `endif
 		else
@@ -21,9 +21,9 @@ module adffn
     end
 	always @( posedge clk, negedge clr )
 		if ( !clr )
-`ifndef BUG        
+`ifndef BUG
 			q <= 1'b0;
-`else        
+`else
 			q <= d;
 `endif
 		else
@@ -35,11 +35,11 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
-`ifndef BUG        
+`ifndef BUG
 			q <= d;
-`else        
+`else
 			q <= 1'b0;
 `endif
 endmodule

architecture/synth_ecp5/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ecp5/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_greenpak4/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_greenpak4/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_ice40/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ice40/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_xilinx/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_xilinx/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/async2sync/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/async2sync/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/clk2fflogic/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/clk2fflogic/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/dff2dffe_unmap/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/dff2dffs/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
 

simple/extract/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
 

simple/flowmap/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/flowmap/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/hierarchy/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/hierarchy/top.v

@@ -47,7 +47,7 @@ module dffe
     initial begin
       q = Z;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/hierarchy_huge/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/hierarchy_huge/top.v

@@ -47,7 +47,7 @@ module dffe
     initial begin
       q = Z;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/prep/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/prep/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/synth/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/synth/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

simple/uniquify/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

simple/uniquify/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 1'bZ;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;