Commit c12353b9 by SergeyDegtyar

Review 'misc' test group (fmcombine,freduce)

parent 05c2477c
read_verilog -sv ../top.v
proc
fmcombine top u_mid1 u_mid3
fmcombine top u_mid2 u_mid4
fmcombine top u_mid1_u_mid3 u_mid2_u_mid4
select -assert-count 1 t:$fmcombine$fmcombine\middle
read_verilog -sv ../top.v
tee -o result.log fmcombine -anyeq top u_mid1 u_mid2
select -assert-count 1 t:$fmcombine\middle
read_verilog -sv ../top_assert_assume.v
tee -o result.log fmcombine -anyeq top u_mid1 u_mid2
read_verilog -sv ../top.v
tee -o result.log fmcombine -anyeq -bwd top u_mid1 u_mid2
read_verilog -sv ../top_assert_assume.v
proc
tee -o res_a.log stat
tee -o result.log fmcombine top u_mid1 u_mid3
tee -o result.log fmcombine top u_mid2 u_mid4
tee -o result.log fmcombine top u_mid1_u_mid3 u_mid2_u_mid4
tee -o res_b.log stat
read_verilog -sv ../top.v
tee -o result.log fmcombine -bwd top u_mid1 u_mid2
select -assert-count 1 t:$fmcombine\middle
read_verilog -sv ../top_assert_assume.v
tee -o result.log fmcombine -bwd top u_mid1 u_mid2
read_verilog -sv ../top.v
tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2
read_verilog -sv ../top_assert_assume.v
tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2
read_verilog -sv ../top_dff.v
proc
tee -o result.log fmcombine -initeq top u_mid1 u_mid3
tee -o result.log fmcombine -initeq top u_mid2 u_mid4
tee -o result.log fmcombine -initeq top u_mid1_u_mid3 u_mid2_u_mid4
select -assert-count 1 t:$fmcombine$fmcombine\middle
read_verilog -sv ../top_dff.v
proc
tee -o res_a.log stat
tee -o result.log fmcombine -bwd top u_mid1 u_mid3
tee -o result.log fmcombine -bwd top u_mid2 u_mid4
tee -o result.log fmcombine -bwd top u_mid1_u_mid3 u_mid2_u_mid4
tee -o res_b.log stat
read_verilog -sv ../top.v
tee -o result.log fmcombine -fwd top u_mid1 u_mid2
select -assert-count 1 t:$fmcombine\middle
read_verilog -sv ../top_assert_assume.v
tee -o result.log fmcombine -fwd top u_mid1 u_mid2
ERROR: Gate cell u_mid8 not found in module top.
read_verilog -sv ../top.v
proc
tee -o result.log fmcombine top u_mid1 u_mid8
ERROR: Gold cell u_mid8 not found in module top.
read_verilog -sv ../top.v
proc
tee -o result.log fmcombine top u_mid8 u_mid3
read_verilog -sv ../top.v
tee -o result.log fmcombine -initeq top u_mid1 u_mid2
select -assert-count 1 t:$fmcombine\middle
read_verilog -sv ../top_assert_assume.v
tee -o result.log fmcombine -initeq top u_mid1 u_mid2
read_verilog -sv ../top.v
proc
tee -o result.log fmcombine
read_verilog -sv ../top.v
proc
tee -o result.log fmcombine topp u_mid1 u_mid3
read_verilog -sv ../top.v
tee -o result.log fmcombine -nop top u_mid1 u_mid2
select -assert-count 1 t:$fmcombine\middle
read_verilog -sv ../top_assert_assume.v
tee -o result.log fmcombine -nop top u_mid1 u_mid2
ERROR: Option -nop can not be combined with -fwd and/or -bwd.
read_verilog -sv ../top.v
tee -o result.log fmcombine -nop -bwd top u_mid1 u_mid2
ERROR: Option -nop can not be combined with -fwd and/or -bwd.
read_verilog -sv ../top.v
tee -o result.log fmcombine -nop -fwd -bwd top u_mid1 u_mid2
ERROR: Option -nop can not be combined with -fwd and/or -bwd.
read_verilog -sv ../top.v
tee -o result.log fmcombine -nop -fwd top u_mid1 u_mid2
ERROR: Types of gold and gate cells do not match.
read_verilog -sv ../top_err_1.v
proc
tee -o result.log fmcombine top u_mid1 u_urtl
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
endmodule
module middle
(
input x,
input y,
output o
);
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.A(o),.y(1'b0));
middle u_mid2 (.x(x),.A(o),.y(1'b1));
middle u_mid3 (.x(x),.A(o),.y(1'bX));
middle u_mid4 (.x(x),.A(o),.y(1'bX));
endmodule
module middle
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.clk(cin),.x(x),.o(o),.y(1'b0));
middle u_mid2 (.clk(cin),.x(x),.o(o),.y(1'b1));
middle u_mid3 (.clk(cin),.x(x),.o(o),.y(1'bX));
middle u_mid4 (.clk(cin),.x(x),.o(o),.y(1'bX));
endmodule
module middle
(
input clk,
input x,
input y,
output o
);
urtl u_urtl (.clk(clk),.x(x),.o(o),.y(y));
endmodule
module urtl
(
input clk,
input x,
input y,
output reg o
);
always @(posedge clk)
o <= x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
parameter U = "string";
wire o;
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module middle
(
input x,
input y,
output o
);
parameter u = 12;
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
read_verilog ../top.v
proc
tee -o result.log freduce
synth
tee -o result.log freduce
read_verilog ../top_dff.v
proc
tee -o result.log freduce
synth
tee -o result.log freduce
read_verilog ../top.v
proc
tee -o result.log freduce -dump fred
read_verilog ../top_ffs.v
proc
tee -o result.log freduce
synth
tee -o result.log freduce
read_verilog ../top_ffs.v
proc
tee -o result.log freduce -inv
synth
tee -o result.log freduce -inv
read_verilog ../top_ffs.v
proc
tee -o result.log freduce -v
synth
tee -o result.log freduce -vv
read_verilog ../top.v
proc
tee -o result.log freduce -inv
read_verilog ../top_err_1.v
tee -o result.log freduce
proc
tee -o result.log freduce
synth
tee -o result.log freduce
read_verilog ../top_mem.v
proc
tee -o result.log freduce
synth
tee -o result.log freduce
read_verilog ../top_mem.v
proc
tee -o result.log freduce -dump dump_a
synth
tee -o result.log freduce -dump dump_b
read_verilog ../top_mem.v
proc
tee -o result.log freduce -inv
synth
tee -o result.log freduce -inv
read_verilog ../top_mem.v
proc
tee -o result.log freduce -stop 1
synth
tee -o result.log freduce -stop 3
read_verilog ../top_mem.v
proc
tee -o result.log freduce -v
synth
tee -o result.log freduce -vv
read_verilog ../top.v
proc
tee -o result.log freduce -stop 1
read_verilog ../top.v
proc
tee -o result.log freduce -v
read_verilog ../top.v
proc
tee -o result.log freduce -vv
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(o),.o(x));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire ll;
assign ll = x & o;
assign o = y & ll;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
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