various issues causing iverilog to give bad result

frontends/read/top.v

@@ -9,11 +9,6 @@ module top
  output cout
  );
 
- initial begin
-    A = 0;
-    cout = 0;
- end
-
 `ifndef BUG
  assign    A =  y + cin;
  assign   cout =  y + A;

frontends/read_aiger/top.v

@@ -9,11 +9,6 @@ module top
  output cout
  );
 
- initial begin
-    A = 0;
-    cout = 0;
- end
-
 `ifndef BUG
  assign    A =  y + cin;
  assign   cout =  y + A;

frontends/verilog_lexer_assert_assume_restrict/testbench.v

 module testbench;
     reg [2:0] in;
 
-	wire patt_out;
-	wire patt_carry_out;
-	wire out;
-    wire carryout;
+	wire patt_out = 0;
+	wire patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/verilog_lexer_assert_assume_restrict/top.v

@@ -5,8 +5,8 @@ module top
  input cin,
  input clk,
 
- output A,
- output cout
+ output reg A,
+ output reg cout
  );
 
  initial begin

frontends/verilog_lexer_unique_priority/top.v

@@ -85,7 +85,8 @@ input [15:0] D,
 output M2,M4,M8,M16
 );
 
-wire a,b,c,d,e,f,g,h;
+wire a,c,d,e,g;
+reg b,h,f;
 
 always @(*)
 begin