Add new tests to simple,misc,architecture

architecture/scripts/anlogic_determine_init_eqn.ys

+read_verilog ../top.v
+read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v
+proc
+flatten
+tribuf -logic
+deminout
+synth -run coarse
+memory_bram -rules +/anlogic/drams.txt
+techmap -map +/anlogic/drams_map.v
+anlogic_determine_init
+opt -fast -mux_undef -undriven -fine
+memory_map
+opt -undriven -fine
+techmap -map +/techmap.v -map +/anlogic/arith_map.v
+dffsr2dff
+techmap -D NO_LUT -map +/anlogic/cells_map.v
+dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit
+opt_expr -mux_undef
+simplemap
+abc -lut 5
+clean
+techmap -map +/anlogic/cells_map.v
+clean
+anlogic_eqn
+write_verilog synth.v

architecture/scripts/ecp5_ffinit.ys

+read_verilog ../top.v
+read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v
+proc
+flatten
+tribuf -logic
+deminout
+synth -run coarse
+memory_bram -rules +/ecp5/bram.txt
+techmap -map +/ecp5/brams_map.v
+opt -fast -mux_undef -undriven -fine
+techmap -map +/techmap.v -map +/ecp5/arith_map.v
+abc -dff
+opt -fast -mux_undef -undriven -fine
+dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
+techmap -D NO_LUT -map +/ecp5/cells_map.v
+opt_expr -mux_undef
+simplemap
+ecp5_ffinit
+write_verilog synth.v

architecture/scripts/synth_coolrunner2_mem.ys

+read_verilog ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v  ../yosys_rocket/SimDTM.v
+#
+synth_coolrunner2
+write_verilog synth.v

architecture/scripts/synth_gowin_nobram.ys

+read_verilog ../top.v
+synth_gowin -nobram
+write_verilog synth.v

architecture/scripts/synth_gowin_noflatten.ys

+read_verilog ../top.v
+synth_gowin -noflatten
+write_verilog synth.v

architecture/synth_anlogic_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [7:0] data_a = 0;
+	reg [5:0] addr_a = 0;
+    reg we_a = 0;
+	wire [7:0] q_a;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.addr_a(addr_a),
+	.we_a(we_a),
+	.clk(clk),
+	.q_a(q_a)
+    );
+
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;
+
+    addr_a <= addr_a + 1;
+    end
+
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a;
+    end
+
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

architecture/synth_anlogic_mem/top.v

+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+			q_a <= ram[addr_a];
+	end
+
+endmodule

architecture/synth_coolrunner2_fulladder/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_coolrunner2_fulladder/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_ecp5_wide_ffs/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk, negedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( !dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+
+    always @( negedge clk, posedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+	assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
+
+endmodule

architecture/synth_ecp5_wide_ffs/top.v

+module adff
+    ( input [3:0] d, input clk, clr, output reg [3:0] q );
+    initial begin
+      q = 4'b0000;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 4'b0110;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input [3:0] d, input clk, clr, output reg [3:0] q );
+    initial begin
+      q = 4'b0100;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 4'b0100;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input [3:0] d, input clk, en, output reg [3:0] q );
+    initial begin
+      q = 4'b0010;
+    end
+	always @( posedge clk)
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 4'b0000;
+`endif
+endmodule
+
+module dffsr
+    ( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 4'b1010;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 4'b0101;
+		else
+            q <= d;
+endmodule
+
+module dffs
+    ( input [3:0] d, input clk, pre, output reg [3:0] q );
+    initial begin
+      q = 1;
+    end
+	always @( posedge clk, negedge pre )
+		if ( !pre )
+			q <= 4'b1111;
+		else
+            q <= d;
+endmodule
+
+
+module dffse
+    ( input [3:0] d, input clk, en, pre, output reg [3:0] q );
+    initial begin
+      q = 1;
+    end
+	always @( posedge clk )
+		if ( !pre )
+			q <= 4'b0101;
+		else
+			if ( en )
+				q <= d;
+endmodule
+
+module ndffnsnr
+    ( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, posedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 4'b0010;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 4'b1101;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input [3:0] a,
+output [3:0] b,b1,b2,b3,b4
+);
+
+wire b5,b6;
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+dffs u_dffs (
+        .clk (clk ),
+        .pre (pre),
+        .d (a ),
+        .q (b5 )
+    );
+
+dffse u_dffse (
+        .clk (clk ),
+        .pre (pre),
+        .en (en),
+        .d (a ),
+        .q (b6 )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_gowin_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [7:0] data_a = 0;
+	reg [5:0] addr_a = 0;
+    reg we_a = 0;
+	wire [7:0] q_a;
+	reg mem_init = 0;
+
+    top uut (
+    data_a[0],
+    data_a[1],
+    data_a[2],
+    data_a[3],
+    data_a[4],
+    data_a[5],
+    data_a[6],
+    data_a[7],
+	addr_a[0],
+	addr_a[1],
+	addr_a[2],
+	addr_a[3],
+	addr_a[4],
+	addr_a[5],
+	we_a,
+	clk,
+	q_a[0],
+	q_a[1],
+	q_a[2],
+	q_a[3],
+	q_a[4],
+	q_a[5],
+	q_a[6],
+	q_a[7]
+    );
+
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;
+
+    addr_a <= addr_a + 1;
+    end
+
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a;
+    end
+
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

architecture/synth_gowin_mem/top.v

+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+			q_a <= ram[addr_a];
+	end
+
+endmodule

architecture/synth_greenpak4_wide_ffs/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        //$dumpfile("testbench.vcd");
+        //$dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk, negedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( !dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= ~dinA[0];
+
+    always @( negedge clk, negedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( negedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= ~dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( negedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+    assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(~dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
+
+endmodule

architecture/synth_greenpak4_wide_ffs/top.v

+module adff
+    ( input [3:0] d, input clk, clr, output reg [3:0] q );
+    initial begin
+      q = 4'b0000;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 4'b0110;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module gp_dff
+    ( input d, input clk, clr, output reg q );
+
+    wire nq;
+
+    GP_DFF u_gp_dffr (d,clk,nq);
+
+    GP_INV u_gp_inv (nq,q);
+
+endmodule
+
+module gp_dffr
+    ( input d, input clk, clr, output reg q );
+
+    wire nq;
+
+    GP_DFFR u_gp_dffr (d,clk,clr,nq);
+
+    GP_INV u_gp_inv (nq,q);
+
+endmodule
+
+module gp_dffs
+    ( input d, input clk, clr, output reg q );
+
+    wire nq;
+
+    GP_DFFS u_gp_dffs (d,clk,clr,nq);
+
+    GP_INV u_gp_inv (nq,q);
+
+endmodule
+
+module gp_dffsi
+    ( input d, input clk, clr, output reg q );
+
+    wire nq;
+
+    GP_DFFSI u_gp_dffs (d,clk,clr,nq);
+
+    GP_INV u_gp_inv (nq,q);
+
+endmodule
+
+module gp_latchs
+    ( input d, input clk, clr, output reg q );
+
+    wire nq;
+
+    GP_DLATCHS u_gp_dffs (d,clk,clr,nq);
+
+    GP_INV u_gp_inv (nq,q);
+
+endmodule
+
+
+module adffn
+    ( input [3:0] d, input clk, clr, output reg [3:0] q );
+    initial begin
+      q = 4'b0100;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 4'b0100;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input [3:0] d, input clk, en, output reg [3:0] q );
+    initial begin
+      q = 4'b0010;
+    end
+	always @( posedge clk)
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 4'b0000;
+`endif
+endmodule
+
+module dffsr
+    ( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 4'b1010;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 4'b0101;
+		else
+            q <= d;
+endmodule
+
+module dffs
+    ( input [3:0] d, input clk, pre, output reg [3:0] q );
+    initial begin
+      q = 1;
+    end
+	always @( posedge clk, negedge pre )
+		if ( !pre )
+			q <= 4'b1111;
+		else
+            q <= d;
+endmodule
+
+
+module dffse
+    ( input [3:0] d, input clk, en, pre, output reg [3:0] q );
+    initial begin
+      q = 1;
+    end
+	always @( posedge clk )
+		if ( !pre )
+			q <= 4'b0101;
+		else
+			if ( en )
+				q <= d;
+endmodule
+
+module ndffnsnr
+    ( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, posedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 4'b0010;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 4'b1101;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input [3:0] a,
+output [3:0] b,b1,b2,b3,b4
+);
+
+wire [3:0] b5,b6,b7,b8,bn,a_i;
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (~a ),
+        .q (bn )
+    );
+
+assign b = ~bn;
+
+dffs u_dffs (
+        .clk (clk ),
+        .pre (pre),
+        .d (a ),
+        .q (b5 )
+    );
+
+gp_dffr u_gp_dffr (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b7[0] )
+    );
+
+gp_dff u_gp_dff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b8[0] )
+    );
+
+gp_dffs u_gp_dffs (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b7[1] )
+    );
+
+gp_dffsi u_gp_dffsi (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b7[2] )
+    );
+
+gp_latchs u_gp_latchs (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b7[3] )
+    );
+
+dffse u_dffse (
+        .clk (clk ),
+        .pre (pre),
+        .en (en),
+        .d (~a ),
+        .q (b6 )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (~clr),
+        .pre (~pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (~clk ),
+        .clr (~clr),
+        .d (~a ),
+        .q (b2 )
+    );
+
+assign a_i[1:0] = a[1:0];
+assign a_i[3:2] = ~a[3:2];
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (~clr),
+        .d (a_i ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (~clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_ice40_mem/init.txt

+/*xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx*/
+@
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

architecture/synth_ice40_mem/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [7:0] data_a = 0;
+	reg [5:0] addr_a = 0;
+    reg we_a = 0;
+	wire [7:0] q_a;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.addr_a(addr_a),
+	.we_a(we_a),
+	.clk(clk),
+	.q_a(q_a)
+    );
+
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;
+
+    addr_a <= addr_a + 1;
+    end
+
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a;
+    end
+
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

architecture/synth_ice40_mem/top.v

+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a,
+	output reg [15:0] q_b,
+	output reg [15:0] q_c
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+			q_a <= ram[addr_a];
+	end
+
+	SB_RAM40_4K #(
+    .READ_MODE(2'h1),
+    .WRITE_MODE(2'h1),
+    .INIT_FILE("init.txt")
+  ) \ram.0.0.0  (
+    .MASK(16'hxxxx),
+    .RADDR({ 5'h00, addr_a }),
+    .RCLK(clk),
+    .RCLKE(1'h1),
+    .RDATA(q_b),
+    .RE(1'h1),
+    .WADDR({ 5'h00, addr_a }),
+    .WCLK(clk),
+    .WCLKE(we_a),
+    .WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
+    .WE(1'h1)
+  );
+
+  	SB_RAM40_4K #(
+    .READ_MODE(2'h1),
+    .WRITE_MODE(2'h1),
+    .INIT_FILE("../init.txt")
+  ) \ram.0.0.1  (
+    .MASK(16'hxxxx),
+    .RADDR({ 5'h00, addr_a }),
+    .RCLK(clk),
+    .RCLKE(1'h1),
+    .RDATA(q_c),
+    .RE(1'h1),
+    .WADDR({ 5'h00, addr_a }),
+    .WCLK(clk),
+    .WCLKE(we_a),
+    .WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
+    .WE(1'h1)
+  );
+
+endmodule

architecture/synth_ice40_wide_ffs/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk, negedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( !dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+
+    always @( negedge clk, posedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+	assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
+
+endmodule

architecture/synth_ice40_wide_ffs/top.v

+module adff
+    ( input [3:0] d, input clk, clr, output reg [3:0] q );
+    initial begin
+      q = 4'b0000;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 4'b0110;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input [3:0] d, input clk, clr, output reg [3:0] q );
+    initial begin
+      q = 4'b0100;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 4'b0100;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input [3:0] d, input clk, en, output reg [3:0] q );
+    initial begin
+      q = 4'b0010;
+    end
+	always @( posedge clk)
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 4'b0000;
+`endif
+endmodule
+
+module dffsr
+    ( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 4'b1010;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 4'b0101;
+		else
+            q <= d;
+endmodule
+
+module dffs
+    ( input [3:0] d, input clk, pre, output reg [3:0] q );
+    initial begin
+      q = 1;
+    end
+	always @( posedge clk, negedge pre )
+		if ( !pre )
+			q <= 4'b1111;
+		else
+            q <= d;
+endmodule
+
+
+module dffse
+    ( input [3:0] d, input clk, en, pre, output reg [3:0] q );
+    initial begin
+      q = 1;
+    end
+	always @( posedge clk )
+		if ( !pre )
+			q <= 4'b0101;
+		else
+			if ( en )
+				q <= d;
+endmodule
+
+module ndffnsnr
+    ( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, posedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 4'b0010;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 4'b1101;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input [3:0] a,
+output [3:0] b,b1,b2,b3,b4
+);
+
+wire b5,b6;
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+dffs u_dffs (
+        .clk (clk ),
+        .pre (pre),
+        .d (a ),
+        .q (b5 )
+    );
+
+dffse u_dffse (
+        .clk (clk ),
+        .pre (pre),
+        .en (en),
+        .d (a ),
+        .q (b6 )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

misc/hilomap/top.v

+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( pre )
+			q <= 1'b1;
+		else if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input a,
+output b,b2
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+`ifndef BUG
+        .clr (1'b0),
+        .pre (1'b1),
+`else
+        .clr (1'b1),
+        .pre (1'b0),
+`endif
+        .d (a ),
+        .q (b )
+    );
+
+dffsr u2_dffsr (
+        .clk (clk ),
+`ifndef BUG
+        .clr (1'b0),
+        .pre (1'b1),
+`else
+        .clr (1'b1),
+        .pre (1'b0),
+`endif
+        .d (a ),
+        .q (b2 )
+    );
+
+endmodule

misc/scripts/hilomap.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap

misc/scripts/hilomap_hicell.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap -hicell VCC V

misc/scripts/hilomap_hicell_locell_singleton.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap -locell GND G -hicell VCC V -singleton

misc/scripts/hilomap_hicell_singleton.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap -hicell VCC V -singleton

misc/scripts/hilomap_locell.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap -locell GND G

misc/scripts/hilomap_locell_singleton.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap -locell GND G -singleton

misc/scripts/hilomap_singleton.ys

+read_verilog ../top.v
+proc
+tee -o result.log hilomap -singleton

simple/prep/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

simple/prep/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

simple/scripts/prep.ys

+read_verilog ../top.v
+prep
+synth -top top
+write_verilog synth.v

simple/scripts/prep_auto_top.ys

+read_verilog ../top.v
+prep -auto-top
+synth -top top
+write_verilog synth.v

simple/scripts/prep_flatten.ys

+read_verilog ../top.v
+prep -flatten
+synth -top top
+write_verilog synth.v

simple/scripts/prep_ifx.ys

+read_verilog ../top.v
+prep -ifx
+synth -top top
+write_verilog synth.v

simple/scripts/prep_memx.ys

+read_verilog ../top.v
+prep -memx
+synth -top top
+write_verilog synth.v

simple/scripts/prep_nokeepdc.ys

+read_verilog ../top.v
+prep -nokeepdc
+synth -top top
+write_verilog synth.v

simple/scripts/prep_nomem.ys

+read_verilog ../top.v
+prep -nomem
+synth -top top
+write_verilog synth.v

simple/scripts/prep_nordff.ys

+read_verilog ../top.v
+prep -nordff
+synth -top top
+write_verilog synth.v

simple/scripts/prep_rdff.ys

+read_verilog ../top.v
+prep -rdff
+synth -top top
+write_verilog synth.v

simple/scripts/prep_run.ys

+read_verilog ../top.v
+prep -run begin:check
+synth -top top
+write_verilog synth.v

simple/scripts/prep_run_begin.ys

+read_verilog ../top.v
+prep -run begin
+synth -top top
+write_verilog synth.v

simple/scripts/prep_top.ys

+read_verilog ../top.v
+prep -top top
+synth -top top
+write_verilog synth.v

simple/scripts/synth.ys

+read_verilog ../top.v
+synth
+write_verilog synth.v

simple/scripts/synth_auto_top.ys

+read_verilog ../top.v
+synth -auto-top
+write_verilog synth.v

simple/scripts/synth_encfile.ys

+read_verilog ../top.v
+synth -encfile enc.file
+write_verilog synth.v

simple/scripts/synth_flatten.ys

+read_verilog ../top.v
+synth -flatten
+write_verilog synth.v

simple/scripts/synth_lut.ys

+read_verilog ../top.v
+synth -lut 5
+write_verilog synth.v

simple/scripts/synth_noabc.ys

+read_verilog ../top.v
+synth -noabc
+write_verilog synth.v

simple/scripts/synth_noabc_lut.ys

+read_verilog ../top.v
+synth -noabc -lut 3
+write_verilog synth.v

simple/scripts/synth_noalumacc.ys

+read_verilog ../top.v
+synth -noalumacc
+write_verilog synth.v

simple/scripts/synth_nofsm.ys

+read_verilog ../top.v
+synth -nofsm
+write_verilog synth.v

simple/scripts/synth_nordff.ys

+read_verilog ../top.v
+synth -nordff
+write_verilog synth.v

simple/scripts/synth_noshare.ys

+read_verilog ../top.v
+synth -noshare
+write_verilog synth.v

simple/scripts/synth_run.ys

+read_verilog ../top.v
+synth -run begin
+write_verilog synth.v

simple/scripts/synth_run_full.ys

+read_verilog ../top.v
+synth -run begin:check
+write_verilog synth.v

simple/scripts/synth_top.ys

+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/synth/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

simple/synth/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule