Fix some failing tests

architecture/synth_gowin/synth_gowin_nodram.ys

@@ -44,7 +44,7 @@ stat
 select -assert-count 520 t:DFF
 select -assert-count 16 t:IBUF
 select -assert-count 592 t:LUT3
-select -assert-min 987 t:LUT4
+select -assert-min 983 t:LUT4
 select -assert-count 464 t:MUX2_LUT5
 select -assert-count 184 t:MUX2_LUT6
 select -assert-count 64 t:MUX2_LUT7

architecture/synth_xilinx/synth_xilinx_nodram.ys

@@ -32,14 +32,14 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
 design -load postopt
 cd top
-
+stat
 select -assert-count 2 t:BUFG
 select -assert-count 390 t:FDRE
 select -assert-count 2 t:LUT2
-select -assert-count 385 t:LUT3
-select -assert-count 9 t:LUT4
-select -assert-count 1 t:LUT5
-select -assert-count 223 t:LUT6
-select -assert-count 36 t:MUXF7
-select -assert-count 3 t:MUXF8
+select -assert-count 384 t:LUT3
+select -assert-count 4 t:LUT4
+select -assert-count 2 t:LUT5
+select -assert-count 214 t:LUT6
+select -assert-count 27 t:MUXF7
+select -assert-count 1 t:MUXF8
 select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D

architecture/synth_xilinx/synth_xilinx_nodsp.ys

@@ -17,14 +17,12 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -noiopad # equiv
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 14 t:LUT2
-select -assert-count 4 t:LUT3
-select -assert-count 4 t:LUT4
-select -assert-count 4 t:LUT5
-select -assert-count 43 t:LUT6
+select -assert-count 17 t:LUT2
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT4
+select -assert-count 2 t:LUT5
+select -assert-count 38 t:LUT6
 select -assert-count 11 t:MUXCY
-select -assert-count 7 t:MUXF7
-select -assert-count 2 t:MUXF8
+select -assert-count 4 t:MUXF7
 select -assert-count 12 t:XORCY
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D

architecture/synth_xilinx/synth_xilinx_nowidelut.ys

@@ -24,12 +24,11 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -noio
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 10 t:LUT2
-select -assert-count 6 t:LUT3
-select -assert-count 5 t:LUT4
-select -assert-count 2 t:LUT5
-select -assert-count 32 t:LUT6
+select -assert-count 17 t:LUT2
+select -assert-count 9 t:LUT3
+select -assert-count 12 t:LUT4
+select -assert-count 7 t:LUT5
+select -assert-count 20 t:LUT6
 select -assert-count 11 t:MUXCY
 select -assert-count 12 t:XORCY
 select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:XORCY %% t:* %D
-

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys

@@ -19,8 +19,8 @@ select -assert-count 2 t:BUFG
 select -assert-count 200 t:FDRE
 select -assert-count 15 t:LUT2
 select -assert-count 68 t:LUT3
-select -assert-count 4 t:LUT4
-select -assert-count 88 t:LUT5
+select -assert-count 5 t:LUT4
+select -assert-count 87 t:LUT5
 select -assert-count 716 t:LUT6
 select -assert-count 328 t:MUXF7
 select -assert-count 148 t:MUXF8