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yosys-tests
Commit adf1f69e by Eddie Hung
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Refactor testing

parent 8175c1c3
Showing with 125 additions and 95 deletions
architecture/run.sh
......@@ -8,6 +8,17 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
run() {
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
}
yosys -ql yosys.log ../../scripts/$2.ys
if [ "$1" = "synth_ecp5" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
......@@ -40,20 +51,29 @@ elif [ "$1" = "synth_sf2" ]; then
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog -o testbench ../testbench.v -I.. ../top.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
iverilog -DTEST1 synth1.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST2 synth2.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST3 synth3.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST4 synth4.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST5 synth5.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST6 synth6.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST7 synth7.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST8 synth8.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog -DTEST9 synth9.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
run
touch .stamp
architecture/synth_xilinx_srl/test2.ys 0 → 100644
read_verilog -icells -DTEST2 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth2.v
architecture/synth_xilinx_srl/test3.ys 0 → 100644
read_verilog -icells -DTEST3 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth3.v
architecture/synth_xilinx_srl/test4.ys 0 → 100644
read_verilog -icells -DTEST4 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth4.v
architecture/synth_xilinx_srl/test5.ys 0 → 100644
read_verilog -icells -DTEST5 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth5.v
architecture/synth_xilinx_srl/test7.ys 0 → 100644
read_verilog -icells -DTEST7 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth7.v
# Check that shift registers with resets are not inferred into SRLs
cd $paramod\template\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\template\inferred=1\init=1\neg_clk=1\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test8.ys 0 → 100644
read_verilog -icells -DTEST8 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth8.v
# Check that wide shift registers are not a problem
cd $paramod\template\width=131\depth=131; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test9.ys 0 → 100644
read_verilog -icells -DTEST9 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth9.v
# Check that wide shift registers are not a problem
cd $paramod\template\width=131\inferred=1\init=1\neg_clk=1\depth=131; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/testbench.v
......@@ -18,35 +18,21 @@ module testbench;
reg [`N-1:0] a;
reg e;
wire [`N-1:0] y1, y2, y3, y4, y5, y6, y9, y10;
wire [`N-1:0] z1, z2, z3, z4, z5, z6, z9, z10;
wire [`N-1:0] y;
wire [`N-1:0] z;
top rtl (
.clk (clk ),
.a (a),
.e (e),
.z1 (y1),
.z2 (y2),
.z3 (y3),
.z4 (y4),
.z5 (y5),
.z6 (y6),
.z9 (y9),
.z10 (y10)
.z (y)
);
synth uut (
.clk (clk ),
.a (a),
.e (e),
.z1 (z1),
.z2 (z2),
.z3 (z3),
.z4 (z4),
.z5 (z5),
.z6 (z6),
.z9 (z9),
.z10 (z10)
.z (z)
);
always @(negedge clk)
......@@ -59,22 +45,8 @@ module testbench;
for (i = 1; i < `N; i=i+1) begin
always @(posedge clk)
a[i] <= $random;
assert_dff z1p_test(.clk(clk), .test(z1[i]), .pat(y1[i]));
assert_dff z1n_test(.clk(~clk), .test(z1[i]), .pat(y1[i]));
assert_dff z2p_test(.clk(clk), .test(z2[i]), .pat(y2[i]));
assert_dff z2n_test(.clk(~clk), .test(z2[i]), .pat(y2[i]));
assert_dff z3p_test(.clk(clk), .test(z3[i]), .pat(y3[i]));
assert_dff z3n_test(.clk(~clk), .test(z3[i]), .pat(y3[i]));
assert_dff z4p_test(.clk(clk), .test(z4[i]), .pat(y4[i]));
assert_dff z4n_test(.clk(~clk), .test(z4[i]), .pat(y4[i]));
assert_dff z5p_test(.clk(clk), .test(z5[i]), .pat(y5[i]));
assert_dff z5n_test(.clk(~clk), .test(z5[i]), .pat(y5[i]));
assert_dff z6p_test(.clk(clk), .test(z6[i]), .pat(y6[i]));
assert_dff z6n_test(.clk(~clk), .test(z6[i]), .pat(y6[i]));
assert_dff z9p_test(.clk(clk), .test(z9[i]), .pat(y9[i]));
assert_dff z9n_test(.clk(~clk), .test(z9[i]), .pat(y9[i]));
assert_dff z10p_test(.clk(clk), .test(z10[i]), .pat(y10[i]));
assert_dff z10n_test(.clk(~clk), .test(z10[i]), .pat(y10[i]));
assert_dff zp_test(.clk(clk), .test(z[i]), .pat(y[i]));
assert_dff zn_test(.clk(~clk), .test(z[i]), .pat(y[i]));
end
endgenerate
......
architecture/synth_xilinx_srl/top.v
`include "defines.vh"
module top(input clk, input [`N-1:0] a, input e, r, output [`N-1:0] z);
generate
genvar i;
`ifdef TEST1
for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
template #(.depth(i+1)) sr(clk, a[i], 1'b1, z[i]);
end
`elsif TEST2
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
template #(.depth(i+1)) sr(clk, a[i], e, z[i]);
end
`elsif TEST3
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
template #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]);
end
`elsif TEST4
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
template #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z[i]);
end
`elsif TEST5
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
template #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, z[i]);
end
`elsif TEST6
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
template #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]);
end
`elsif TEST7
// Check that use of resets block shreg
(* keep *)
template #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[0], r, z[0]);
(* keep *)
template #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[1], r, z[1]);
assign z[`N-1:2] = 'b0; // Suppress no driver warning
`elsif TEST8
// Check multi-bit works
(* keep *)
template #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, z);
`elsif TEST9
(* keep *)
template #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, z);
`endif
endgenerate
endmodule
module template #(parameter width=1) (input clk, input [width-1:0] a, input er, output [width-1:0] z);
parameter inferred = 0;
parameter init = 0;
......@@ -83,56 +128,4 @@ generate
endgenerate
endmodule
module top(input clk, input [`N-1:0] a, input e, r, output [`N-1:0] z1, z2, z3, z4, z5, z6, z7, z8, z9, z10);
generate
genvar i;
for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
if (i <= 1 || i == 14 || i == 15 || i == 16 || i == 30 || i == 31 ||
i == 46 || i == 47 || i == 62 || i == 63 || i == 78 || i == 79 ||
i == 94 || i == 95 || i == 100 || i == 101 || i >= 126)
template #(.depth(i+1)) sr(clk, a[i], 1'b1, z1[i]);
end
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
if (i<= 1 || i == 14 || i == 15 || i == 16 || i == 30 || i == 31 ||
i == 46 || i == 47 || i == 62 || i == 63 || i == 78 || i == 79 ||
i == 94 || i == 95 || i == 100 || i == 101 || i >= 126)
template #(.depth(i+1)) sr(clk, a[i], e, z2[i]);
end
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
if (i <= 1 || i == 14 || i == 15 || i == 16 || i == 30 || i == 31 ||
i == 46 || i == 47 || i == 62 || i == 63 || i == 78 || i == 79 ||
i == 94 || i == 95 || i == 100 || i == 101 || i >= 126)
template #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, z3[i]);
end
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
if (i <= 1 || i == 14 || i == 15 || i == 16 || i == 30 || i == 31 ||
i == 46 || i == 47 || i == 62 || i == 63 || i == 78 || i == 79 ||
i == 94 || i == 95 || i == 100 || i == 101 || i >= 126)
template #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z4[i]);
end
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
if (i <= 1 || i == 14 || i == 15 || i == 16 || i == 30 || i == 31 ||
i == 46 || i == 47 || i == 62 || i == 63 || i == 78 || i == 79 ||
i == 94 || i == 95 || i == 100 || i == 101 || i >= 126)
template #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, z5[i]);
end
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
if (i <= 1 || i == 14 || i == 15 || i == 16 || i == 30 || i == 31 ||
i == 46 || i == 47 || i == 62 || i == 63 || i == 78 || i == 79 ||
i == 94 || i == 95 || i == 100 || i == 101 || i >= 126)
template #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z6[i]);
end
// Check that use of resets block shreg
(* keep *)
template #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[`N-1], r, z7[`N-1]);
(* keep *)
template #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[`N-1], r, z8[`N-1]);
// Check multi-bit works
(* keep *)
template #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, z9);
(* keep *)
template #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, z10);
endgenerate
endmodule
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