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lvzhengyang
yosys-tests
Commits
ab07a8d5
Commit
ab07a8d5
authored
Jun 29, 2019
by
Miodrag Milanovic
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Fix test cases according to new naming
parent
d5339b41
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2 changed files
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6 additions
and
6 deletions
+6
-6
frontends/read_aiger_ff/testbench.v
+4
-4
frontends/read_aiger_latch/testbench.v
+2
-2
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frontends/read_aiger_ff/testbench.v
View file @
ab07a8d5
...
...
@@ -22,10 +22,10 @@ module testbench;
top
uut
(
.
clk
(
clk
)
,
.
n1
(
n1
)
,
.
n2
(
n2
)
,
.
n3
(
n3
)
,
.
n3_inv
(
n3_inv
)
.
__1__
(
n1
)
,
.
__2__
(
n2
)
,
.
__3__
(
n3
)
,
.
__3
b__
(
n3_inv
)
)
;
always
@
(
posedge
clk
)
begin
...
...
frontends/read_aiger_latch/testbench.v
View file @
ab07a8d5
...
...
@@ -21,8 +21,8 @@ module testbench;
top
uut
(
.
clk
(
en
)
,
//.
n1
(dinA ),
.
n1_inv
(
doutB
)
//.
__1__
(dinA ),
.
__1
b__
(
doutB
)
)
;
always
@
(
posedge
en
)
begin
...
...
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