Add new tests to 'simple' and 'misc' groups.

backends
=======
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419

simple
=========
+ 1. passes/techmap/attrmap.cc
There is example in help block create example with
(* keep="true" *) attribute and run example

+ 2. passes/techmap/dff2dffe.cc
execute with  -unmap parameter

+ 3. passes/techmap/dff2dffs.cc

+ 4. passes/techmap/extract.cc
Lot of variations of input parameters is not excersised

? 5. passes/techmap/extract_counter.cc
This is specific to greenpak4 architecture, but idea is to have counter
in design and call this after synth_greenpak

+ 6. passes/techmap/shregmap.cc.
This also seams to be greenpak4 specific, but extracting shift register

misc
========
1. passes/techmap/insbuf.cc

Testing problems:
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419
2.dff2dffe -direct - skipped: ERROR: Found error in internal cell
\dffe.$procdff$47 ($dffe) at
3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal
cell

misc/Makefile

@@ -69,4 +69,7 @@ $(eval $(call template,delete_mem, delete_mem ))
 #cover
 $(eval $(call template,cover, cover cover_q cover_o cover_dir cover_a ))
 
+#insbuf ERROR: Found error in internal cell
+#$(eval $(call template,insbuf,insbuf insbuf_cell))
+
 .PHONY: all clean

misc/insbuf/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg in;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .in(in),
+              .out(f));
+
+    always @(posedge clk) begin
+    #3
+    in <= ~in;
+    end
+
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

misc/insbuf/top.v

+module top    (
+out,
+i,
+clk,
+o,
+in
+);
+    output [7:0] out;
+    input clk, in;
+    reg [7:0] out;
+    input i;
+    output o;
+
+    always @(posedge clk)
+	begin
+		out    <= out << 1;
+		out[0] <= in;
+	end
+
+endmodule

misc/scripts/insbuf.ys

+read_verilog ../top.v
+synth
+insbuf
+write_verilog synth.v

misc/scripts/insbuf_cell.ys

+read_verilog ../top.v
+synth
+insbuf -buf $_BUF_ in out
+write_verilog synth.v

simple/Makefile

@@ -83,4 +83,29 @@ $(eval $(call template,uniquify,uniquify))
 #hierarchy (44% increased to 61,3%)
 $(eval $(call template,hierarchy,hierarchy hierarchy_top hierarchy_check hierarchy_simcheck hierarchy_purge_lib hierarchy_libdir hierarchy_keep_positionals hierarchy_keep_portwidths hierarchy_nokeep_asserts hierarchy_auto_top hierarchy_generate))
 
+#attrmap
+$(eval $(call template,attrmap,attrmap attrmap_modattr))
+
+#dff2dffe -unmap
+# dff2dffe_unmap_direct - skipped: ERROR: Found error in internal cell \dffe.$procdff$47 ($dffe) at
+$(eval $(call template,dff2dffe_unmap,dff2dffe_unmap dff2dffe_unmap_mince))
+
+#dff2dffs
+$(eval $(call template,dff2dffs,dff2dffs))
+
+#extract
+$(eval $(call template,extract,extract_cell_attr extract_compat extract_constports extract_map_design extract_ignore_parameters extract_ignore_param  extract_map extract_mine_cells_span extract_mine_limit_matches_per_module extract_mine_max_fanout extract_mine_min_freq extract_mine_split extract_mine extract_nodefaultswaps extract_perm extract_swap extract_verbose extract_wire_attr ))
+
+#extract_counter
+$(eval $(call template,extract_counter,extract_counter extract_counter_maxwidth extract_counter_pout))
+$(eval $(call template,extract_counter_down,extract_counter extract_counter_maxwidth extract_counter_pout))
+$(eval $(call template,extract_counter_negative_reset,extract_counter extract_counter_maxwidth extract_counter_pout))
+$(eval $(call template,extract_counter_no_reset,extract_counter extract_counter_maxwidth extract_counter_pout))
+$(eval $(call template,extract_counter_sync_reset,extract_counter extract_counter_maxwidth extract_counter_pout))
+
+#shregmap
+$(eval $(call template,shregmap,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
+$(eval $(call template,shregmap_resetable,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
+
+
 .PHONY: all clean

simple/attrmap/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg dinA = 0;
+    wire doutB;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (doutB )
+    );
+
+    always @(posedge en) begin
+    //#3;
+    dinA <= !dinA;
+    end
+
+	assert_tri b_test(.en(en), .A(dinA), .B(doutB));
+
+endmodule

simple/attrmap/top.v

+module top (en, a, b);
+    input en;
+	input a;
+	output reg b;
+
+    (* keep = "true" *) wire  int_dat;
+`ifndef BUG
+
+    always @(en or a)
+		b <= (en)? a : 1'bZ;
+`else
+
+    always @(en or a)
+		b <= (en)? ~a : 1'bZ;
+`endif
+endmodule

simple/dff2dffe_unmap/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

simple/dff2dffe_unmap/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

simple/dff2dffs/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk)
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+
+    always @( negedge clk)
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+
+endmodule

simple/dff2dffs/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk)
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk)
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

simple/extract/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk)
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+
+    always @( negedge clk)
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+
+endmodule

simple/extract/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk)
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk)
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

simple/extract_counter/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .reset(rst),
+              .out(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/extract_counter/top.v

+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (reset) begin
+			out <= 8'b0 ;
+		end else
+			out <= out + 1;
+
+
+endmodule

simple/extract_counter_down/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .reset(rst),
+              .out(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/extract_counter_down/top.v

+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (reset) begin
+			out <= 8'b11111111;
+		end else
+			out <= out - 1;
+
+
+endmodule

simple/extract_counter_negative_reset/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .reset(rst),
+              .out(f));
+
+    initial begin
+        rst <= 0;
+        #5
+        rst <= 1;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/extract_counter_negative_reset/top.v

+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (!reset) begin
+			out <= 8'b00000000;
+		end else
+			out <= out + 1;
+
+
+endmodule

simple/extract_counter_no_reset/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .reset(rst),
+              .out(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/extract_counter_no_reset/top.v

+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+	initial out <= 0 ;
+
+
+    always @(posedge clk)
+			out <= out + 1;
+
+
+endmodule

simple/extract_counter_sync_reset/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .reset(rst),
+              .out(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/extract_counter_sync_reset/top.v

+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk)
+		if (reset) begin
+			out <= 8'b0 ;
+		end else
+			out <= out + 1;
+
+
+endmodule

simple/scripts/attrmap.ys

+read_verilog ../top.v
+proc
+attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
+write_verilog synth.v

simple/scripts/attrmap_modattr.ys

+read_verilog ../top.v
+proc
+attrmap -modattr -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 -rename keep keep_attr
+write_verilog synth.v

simple/scripts/dff2dffe_unmap.ys

+read_verilog ../top.v
+proc
+dff2dffe
+dff2dffe -unmap
+synth -top top
+dff2dffe
+dff2dffe -unmap
+flatten
+opt
+opt_rmdff
+write_verilog synth.v

simple/scripts/dff2dffe_unmap_direct.ys

+read_verilog ../top.v
+proc
+dff2dffe -direct $dff $dffe
+dff2dffe -unmap
+synth -top top
+dff2dffe -direct $dff $dffe
+dff2dffe -unmap
+flatten
+opt
+opt_rmdff
+write_verilog synth.v

simple/scripts/dff2dffe_unmap_mince.ys

+read_verilog ../top.v
+proc
+dff2dffe
+dff2dffe -unmap-mince 2
+synth -top top
+dff2dffe
+dff2dffe -unmap-mince 2
+flatten
+opt
+opt_rmdff
+write_verilog synth.v

simple/scripts/dff2dffs.ys

+read_verilog ../top.v
+proc
+techmap
+dff2dffs
+design -reset
+read_verilog ../top.v
+synth -top top
+flatten
+opt
+opt_rmdff
+write_verilog synth.v

simple/scripts/extract_cell_attr.ys

+read_verilog ../top.v
+extract -map ../top.v -cell_attr attr
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_compat.ys

+read_verilog ../top.v
+extract -map ../top.v -compat $dff a
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_constports.ys

+read_verilog ../top.v
+extract -map ../top.v -constports
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_counter.ys

+read_verilog ../top.v
+synth_greenpak4
+extract_counter
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/extract_counter_maxwidth.ys

+read_verilog ../top.v
+synth_greenpak4
+extract_counter -maxwidth 4
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/extract_counter_pout.ys

+read_verilog ../top.v
+synth_greenpak4
+extract_counter -pout X
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/extract_ignore_param.ys

+read_verilog ../top.v
+extract -map ../top.v -ignore_param $dff param
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_ignore_parameters.ys

+read_verilog ../top.v
+extract -map ../top.v  -ignore_parameters
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_map.ys

+read_verilog ../top.v
+extract -map ../top.v
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_map_design.ys

+read_verilog ../top.v
+design -save top_test
+extract -map %top_test
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_mine.ys

+read_verilog ../top.v
+extract -mine out.ilang
+write_verilog synth.v

simple/scripts/extract_mine_cells_span.ys

+read_verilog ../top.v
+extract  -mine out.ilang -mine_cells_span 3 5
+write_verilog synth.v

simple/scripts/extract_mine_limit_matches_per_module.ys

+read_verilog ../top.v
+extract  -mine out.ilang -mine_limit_matches_per_module 5
+write_verilog synth.v

simple/scripts/extract_mine_max_fanout.ys

+read_verilog ../top.v
+extract  -mine out.ilang -mine_max_fanout 2
+write_verilog synth.v

simple/scripts/extract_mine_min_freq.ys

+read_verilog ../top.v
+extract  -mine out.ilang -mine_min_freq 10
+write_verilog synth.v

simple/scripts/extract_mine_split.ys

+read_verilog ../top.v
+extract  -mine out.ilang -mine_split 2 2
+write_verilog synth.v

simple/scripts/extract_nodefaultswaps.ys

+read_verilog ../top.v
+extract  -map ../top.v -nodefaultswaps
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_perm.ys

+read_verilog ../top.v
+extract  -map ../top.v -perm $dff D,CLK D,CLK
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_swap.ys

+read_verilog ../top.v
+extract  -map ../top.v -swap $dff D,CLK
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_verbose.ys

+read_verilog ../top.v
+extract  -map ../top.v -verbose
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/extract_wire_attr.ys

+read_verilog ../top.v
+extract  -map ../top.v -wire_attr attr
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/shregmap.ys

+read_verilog ../top.v
+synth_greenpak4
+shregmap
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_clkpol_any.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -clkpol any
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_clkpol_neg.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -clkpol neg
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_clkpol_pos.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -clkpol pos
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_enpol_any.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -enpol any
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_enpol_any_or_none.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -enpol any_or_none
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_enpol_neg.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -enpol neg
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_enpol_none.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -enpol none
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_enpol_pos.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -enpol pos
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_init.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -init
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_keep_after.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -keep_after 5
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_keep_before.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -keep_before 3
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_match.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -match \GP_DFF
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_maxlen.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -maxlen 10
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_minlen.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -minlen 4
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_params.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4 -params
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_tech.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -tech greenpak4
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/scripts/shregmap_zinit.ys

+read_verilog ../top.v
+synth_greenpak4 -run begin:map_luts
+shregmap -zinit
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

simple/shregmap/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg in;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .in(in),
+              .out(f));
+
+    always @(posedge clk) begin
+    #3
+    in <= ~in;
+    end
+
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/shregmap/top.v

+module top    (
+out,
+clk,
+in
+);
+    output [7:0] out;
+    input clk, in;
+    reg [7:0] out;
+
+    always @(posedge clk)
+	begin
+		out    <= out << 1;
+		out[0] <= in;
+	end
+
+endmodule

simple/shregmap_resetable/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg in;
+    reg rst;
+    wire f;
+
+
+    top #(8) uut  ( .clk(clk),
+			  .reset(rst),
+              .s_in(in),
+              .s_out(f));
+
+    always @(posedge clk) begin
+    #3
+    in <= ~in;
+    end
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/shregmap_resetable/top.v

+module top
+   #(parameter N=8)
+   (
+    input wire clk, reset,
+    input wire s_in,
+    output wire s_out
+   );
+
+   reg [N-1:0] r_reg;
+   wire [N-1:0] r_next;
+
+
+   always @(posedge clk, negedge reset)
+   begin
+      if (~reset)
+         r_reg <= 0;
+      else
+         r_reg <= r_next;
+	end
+
+	assign r_next = {s_in, r_reg[N-1:1]};
+	assign s_out = r_reg[0];
+
+
+endmodule