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lvzhengyang
yosys-tests
Commits
a76ad5a7
Commit
a76ad5a7
authored
Jul 10, 2019
by
SergeyDegtyar
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Rename pr_896 to issue_896
parent
d05351de
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5 changed files
with
3 additions
and
3 deletions
+3
-3
regression/Makefile
+2
-2
regression/issue_00896/outreg.v
+0
-0
regression/issue_00896/testbench.v
+0
-0
regression/run.sh
+1
-1
regression/scripts/issue_00896.ys
+0
-0
No files found.
regression/Makefile
View file @
a76ad5a7
...
@@ -353,8 +353,8 @@ $(eval $(call template,issue_00873,issue_00873))
...
@@ -353,8 +353,8 @@ $(eval $(call template,issue_00873,issue_00873))
#issue_00888
#issue_00888
$(eval
$(call
template,issue_00888,issue_00888))
$(eval
$(call
template,issue_00888,issue_00888))
#
pr
_00896
#
issue
_00896
$(eval
$(call
template,
pr_00896,pr
_00896))
$(eval
$(call
template,
issue_00896,issue
_00896))
#issue_00922
#issue_00922
$(eval
$(call
template,issue_00922,issue_00922))
$(eval
$(call
template,issue_00922,issue_00922))
...
...
regression/
pr
_00896/outreg.v
→
regression/
issue
_00896/outreg.v
View file @
a76ad5a7
File moved
regression/
pr
_00896/testbench.v
→
regression/
issue
_00896/testbench.v
View file @
a76ad5a7
File moved
regression/run.sh
View file @
a76ad5a7
...
@@ -294,7 +294,7 @@ else
...
@@ -294,7 +294,7 @@ else
[
"
$1
"
=
"issue_00589"
]
||
\
[
"
$1
"
=
"issue_00589"
]
||
\
[
"
$1
"
=
"issue_00628"
]
;
then
[
"
$1
"
=
"issue_00628"
]
;
then
iverilog_adds
=
"
$TECHLIBS_PREFIX
/ice40/cells_sim.v"
iverilog_adds
=
"
$TECHLIBS_PREFIX
/ice40/cells_sim.v"
elif
[
"
$1
"
=
"
pr
_00896"
]
;
then
elif
[
"
$1
"
=
"
issue
_00896"
]
;
then
iverilog_adds
=
"
$TECHLIBS_PREFIX
/ecp5/cells_sim.v"
iverilog_adds
=
"
$TECHLIBS_PREFIX
/ecp5/cells_sim.v"
fi
fi
...
...
regression/scripts/
pr
_00896.ys
→
regression/scripts/
issue
_00896.ys
View file @
a76ad5a7
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