Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Commits
9f7dd41b
Commit
9f7dd41b
authored
Mar 20, 2019
by
Eddie Hung
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Makefile based approach
parent
0a519631
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
52 additions
and
65 deletions
+52
-65
architecture/run.sh
+18
-21
architecture/synth_xilinx_srl/Makefile
+33
-0
architecture/synth_xilinx_srl/run.sh
+0
-2
architecture/synth_xilinx_srl/top.v
+1
-1
architecture/synth_xilinx_srl/yosys.ys
+0
-41
No files found.
architecture/run.sh
View file @
9f7dd41b
...
...
@@ -8,21 +8,11 @@ rm -rf $1/work_$2
mkdir
$1
/work_
$2
cd
$1
/work_
$2
run
()
{
if
!
vvp
-N
testbench
>
testbench.log 2>&1
;
then
grep
'ERROR'
testbench.log
echo
fail
>
${
1
}
_
${
2
}
.status
elif
grep
'ERROR'
testbench.log
||
!
grep
'OKAY'
testbench.log
;
then
echo
fail
>
${
1
}
_
${
2
}
.status
else
echo
pass
>
${
1
}
_
${
2
}
.status
fi
}
if
[
-f
../run.sh
]
;
then
../run.sh
if
[
-f
../Makefile
]
;
then
make
-C
..
else
yosys
-ql
yosys.log ../../scripts/
$2
.ys
fi
yosys
-ql
yosys.log ../../scripts/
$2
.ys
if
[
"
$1
"
=
"synth_ecp5"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
elif
[
"
$1
"
=
"synth_achronix"
]
;
then
...
...
@@ -54,18 +44,25 @@ elif [ "$1" = "synth_sf2" ]; then
elif
[
"
$1
"
=
"synth_xilinx"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif
[
"
$1
"
=
"synth_xilinx_srl"
]
;
then
i
verilog
-DTEST1
synth1.v
-o
testbench ../testbench.v
-I
.. ../top.v ../lfsr.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
for
i
in
{
2..14
}
;
do
run
yosys
-ql
yosys.log
-p
"script ../yosys.ys TEST
$i
"
iverilog
-DTEST
$i
synth
$i
.v
-o
testbench ../testbench.v
-I
.. ../top.v ../lfsr.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
done
i
f
grep
'fail'
*
.status
;
then
echo
fail
>
${
1
}
_
${
2
}
.status
else
echo
pass
>
${
1
}
_
${
2
}
.status
fi
exit
elif
[
"
$1
"
=
"synth_greenpak4"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
fi
run
if
!
vvp
-N
testbench
>
testbench.log 2>&1
;
then
grep
'ERROR'
testbench.log
echo
fail
>
${
1
}
_
${
2
}
.status
elif
grep
'ERROR'
testbench.log
||
!
grep
'OKAY'
testbench.log
;
then
echo
fail
>
${
1
}
_
${
2
}
.status
else
echo
pass
>
${
1
}
_
${
2
}
.status
fi
touch .stamp
architecture/synth_xilinx_srl/Makefile
0 → 100644
View file @
9f7dd41b
OUTDIR
:=
work_synth_xilinx_srl
YS
:=
$
(
wildcard
*
.ys
)
TARGETS
:=
$
(
patsubst %.ys,
$(OUTDIR)
/%.status,
$(YS)
)
.PHONY
:
all
all
:
$(TARGETS)
echo
ALL PASSED!
$(OUTDIR)/test%.status
:
cd
$(OUTDIR)
&&
yosys
-ql
yosys
$*
.log ../test
$*
.ys
iverilog
-DTEST
$*
$(OUTDIR)
/synth
$*
.v
-o
$(OUTDIR)
/testbench
$*
testbench.v top.v ../common.v ../../../../techlibs/common/simcells.v ../../../../techlibs/xilinx/cells_sim.v
if
!
vvp
-N
$(OUTDIR)
/testbench
$*
>
$(OUTDIR)
/testbench
$*
.log 2>&1
;
then
\
grep
'ERROR'
$(OUTDIR)
/testbench
$*
.log
;
\
echo
fail
>
$@
;
\
elif
grep
'ERROR'
$(OUTDIR)
/testbench
$*
.log
||
!
grep
'OKAY'
$(OUTDIR)
/testbench
$*
.log
;
then
\
echo
fail
>
$@
;
\
else
\
echo
pass
>
$@
;
\
fi
$(OUTDIR)/test12.status
:
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py
-O
lfsr_generate.py
python3 lfsr_generate.py
cd
$(OUTDIR)
&&
yosys
-ql
yosys12.log ../test12.ys
iverilog
-DTEST12
$(OUTDIR)
/synth12.v
-o
$(OUTDIR)
/testbench12 testbench.v top.v lfsr.v ../common.v ../../../../techlibs/common/simcells.v ../../../../techlibs/xilinx/cells_sim.v
if
!
vvp
-N
$(OUTDIR)
/testbench12
>
$(OUTDIR)
/testbench12.log 2>&1
;
then
\
grep
'ERROR'
$(OUTDIR)
/testbench12.log
;
\
echo
fail
>
$(OUTDIR)
/test12.status
;
\
elif
grep
'ERROR'
$(OUTDIR)
/testbench12.log
||
!
grep
'OKAY'
$(OUTDIR)
/testbench12.log
;
then
\
echo
fail
>
$(OUTDIR)
/test12.status
;
\
else
\
echo
pass
>
$(OUTDIR)
/test12.status
;
\
fi
architecture/synth_xilinx_srl/run.sh
deleted
100755 → 0
View file @
0a519631
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py
-O
lfsr_generate.py
python3 lfsr_generate.py
architecture/synth_xilinx_srl/top.v
View file @
9f7dd41b
...
...
@@ -123,7 +123,7 @@ generate
if
(
init
)
begin
genvar
i
;
for
(
i
=
0
;
i
<
depth
;
i
=
i
+
1
)
initial
int
[
j
][
i
]
=
~
((
i
+
j
)
%
2
)
;
initial
int
[
j
][
i
]
<
=
~
((
i
+
j
)
%
2
)
;
end
if
(
depth
==
1
)
begin
...
...
architecture/synth_xilinx_srl/yosys.ys
deleted
100644 → 0
View file @
0a519631
TEST1:
script ../test1.ys
TEST2:
script ../test2.ys
TEST3:
script ../test3.ys
TEST4:
script ../test4.ys
TEST5:
script ../test5.ys
TEST6:
script ../test6.ys
TEST7:
script ../test7.ys
TEST8:
script ../test8.ys
TEST9:
script ../test9.ys
TEST10:
script ../test10.ys
TEST11:
script ../test11.ys
TEST12:
script ../test12.ys
TEST13:
script ../test13.ys
TEST14:
script ../test14.ys
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment