Commit 9f7dd41b by Eddie Hung

Makefile based approach

parent 0a519631
......@@ -8,21 +8,11 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
run() {
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
}
if [ -f ../run.sh ]; then
../run.sh
if [ -f ../Makefile ]; then
make -C ..
else
yosys -ql yosys.log ../../scripts/$2.ys
fi
yosys -ql yosys.log ../../scripts/$2.ys
if [ "$1" = "synth_ecp5" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
elif [ "$1" = "synth_achronix" ]; then
......@@ -54,18 +44,25 @@ elif [ "$1" = "synth_sf2" ]; then
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog -DTEST1 synth1.v -o testbench ../testbench.v -I.. ../top.v ../lfsr.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
for i in {2..14}; do
run
yosys -ql yosys.log -p "script ../yosys.ys TEST$i"
iverilog -DTEST$i synth$i.v -o testbench ../testbench.v -I.. ../top.v ../lfsr.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
done
if grep 'fail' *.status; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
exit
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
fi
run
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
touch .stamp
OUTDIR := work_synth_xilinx_srl
YS := $(wildcard *.ys)
TARGETS := $(patsubst %.ys,$(OUTDIR)/%.status,$(YS))
.PHONY: all
all: $(TARGETS)
echo ALL PASSED!
$(OUTDIR)/test%.status:
cd $(OUTDIR) && yosys -ql yosys$*.log ../test$*.ys
iverilog -DTEST$* $(OUTDIR)/synth$*.v -o $(OUTDIR)/testbench$* testbench.v top.v ../common.v ../../../../techlibs/common/simcells.v ../../../../techlibs/xilinx/cells_sim.v
if ! vvp -N $(OUTDIR)/testbench$* > $(OUTDIR)/testbench$*.log 2>&1; then \
grep 'ERROR' $(OUTDIR)/testbench$*.log; \
echo fail > $@; \
elif grep 'ERROR' $(OUTDIR)/testbench$*.log || ! grep 'OKAY' $(OUTDIR)/testbench$*.log; then \
echo fail > $@; \
else \
echo pass > $@; \
fi
$(OUTDIR)/test12.status:
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O lfsr_generate.py
python3 lfsr_generate.py
cd $(OUTDIR) && yosys -ql yosys12.log ../test12.ys
iverilog -DTEST12 $(OUTDIR)/synth12.v -o $(OUTDIR)/testbench12 testbench.v top.v lfsr.v ../common.v ../../../../techlibs/common/simcells.v ../../../../techlibs/xilinx/cells_sim.v
if ! vvp -N $(OUTDIR)/testbench12 > $(OUTDIR)/testbench12.log 2>&1; then \
grep 'ERROR' $(OUTDIR)/testbench12.log; \
echo fail > $(OUTDIR)/test12.status; \
elif grep 'ERROR' $(OUTDIR)/testbench12.log || ! grep 'OKAY' $(OUTDIR)/testbench12.log; then \
echo fail > $(OUTDIR)/test12.status; \
else \
echo pass > $(OUTDIR)/test12.status; \
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O lfsr_generate.py
python3 lfsr_generate.py
......@@ -123,7 +123,7 @@ generate
if (init) begin
genvar i;
for (i = 0; i < depth; i=i+1)
initial int[j][i] = ~((i+j) % 2);
initial int[j][i] <= ~((i+j) % 2);
end
if (depth == 1) begin
......
TEST1:
script ../test1.ys
TEST2:
script ../test2.ys
TEST3:
script ../test3.ys
TEST4:
script ../test4.ys
TEST5:
script ../test5.ys
TEST6:
script ../test6.ys
TEST7:
script ../test7.ys
TEST8:
script ../test8.ys
TEST9:
script ../test9.ys
TEST10:
script ../test10.ys
TEST11:
script ../test11.ys
TEST12:
script ../test12.ys
TEST13:
script ../test13.ys
TEST14:
script ../test14.ys
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