Commit 9e9090ef by SergeyDegtyar

Add tests for abc9 command; Add tests for passes/techmap commands;

parent 03487ce0
......@@ -269,7 +269,11 @@ $(eval $(call template,script, script script_from_to script_scriptwire ))
$(eval $(call template,tcl, tcl ))
#abc9
$(eval $(call template,abc9, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D ))
$(eval $(call template,abc9, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth abc9_box abc9_script))
$(eval $(call template,abc9_dff, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth))
$(eval $(call template,abc9_mux, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth))
$(eval $(call template,abc9_mem, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth))
$(eval $(call template,abc9_error, abc9_invalid_luts_syntax abc9_cant_open_output_file))
.PHONY: all clean
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
module top (
input [7:0] S,
input [255:0] D,
output M256
);
assign M256 = D[S];
endmodule
......@@ -378,6 +378,10 @@ if echo "$1" | grep ".*_error"; then
elif [ "$2" = "write_file_missing_name" ] || \
[ "$2" = "write_file_a_missing_name" ]; then
expected_string="ERROR: Missing output filename."
elif [ "$2" = "abc9_invalid_luts_syntax" ]; then
expected_string="ERROR: Invalid -luts syntax."
elif [ "$2" = "abc9_cant_open_output_file" ]; then
expected_string="ERROR: Can't open ABC output file"
fi
......
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -W -lut 2
tee -o result.log abc9 -box box.txt -lut 2
read_verilog ../top.v
tee -o result.log abc9 -luts uu
read_verilog ../top.v
tee -o result.log abc9 -luts 2:2:2:/2
tee -o result.log abc9 -script box.txt -lut 2
read_verilog ../top.v
tee -o result.log abc9 -lut 2
read_verilog ../top.v
proc
tee -o result.log abc9 -lut 2
......@@ -64,7 +64,7 @@ $(eval $(call template,fsm, fsm))
$(eval $(call template,fsm_opt, fsm))
#Extract full and half adders
$(eval $(call template,full_adder,full_adder half_adder))
$(eval $(call template,full_adder,full_adder half_adder full_adder_d full_adder_b full_adder_wo_opt))
#Extract reduce
$(eval $(call template,reduce,reduce reduce_allow_off_chain))
......@@ -84,7 +84,7 @@ $(eval $(call template,clk2fflogic_latch,clk2fflogic))
$(eval $(call template,clk2fflogic_mem,clk2fflogic_mem))
#muxcover
$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode))
$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode muxcover_mux2 muxcover_dmux))
$(eval $(call template,muxcover_mux8,muxcover_mux8 muxcover_mux8_nodecode))
#aigmap
......@@ -143,7 +143,7 @@ $(eval $(call template,flowmap_latch,flowmap flowmap_cells flowmap_debug_relax f
$(eval $(call template,flowmap_mem,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
#iopadmap
$(eval $(call template,iopadmap,iopadmap))
$(eval $(call template,iopadmap,iopadmap iopadmap_dont_map))
#tribuf
$(eval $(call template,tribuf,tribuf tribuf_top tribuf_merge_top))
......@@ -227,5 +227,12 @@ $(eval $(call template_error, prep_error, prep_error))
$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare))
$(eval $(call template_error, synth_error, synth_error))
#simplemap
$(eval $(call template, simplemap, simplemap simplemap_top simplemap_slice_concat))
$(eval $(call template, simplemap_reduce, simplemap simplemap_top simplemap_slice_concat))
$(eval $(call template, simplemap_mem_slice_concat, simplemap simplemap_top simplemap_slice_concat))
#techmap
$(eval $(call template, techmap, techmap techmap_wb techmap_autoproc techmap_recursive techmap_extern techmap_assert techmap_i techmap_d techmap_max_iter techmap_map))
.PHONY: all clean
read_verilog ../top.v
synth -top top
extract_fa -fa -b 12 top
tee -o result.log dump
synth -top top
write_verilog synth.v
read_verilog ../top.v
synth -top top
extract_fa -fa -d 6 top
tee -o result.log dump
synth -top top
write_verilog synth.v
read_verilog ../top.v
synth -top top
extract_fa
tee -o result.log dump
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
iopadmap -widthparam wp
iopadmap -nameparam np
iopadmap -bits
iopadmap -inpad IBUF O:I
iopadmap -outpad IOBUFE O:IO
iopadmap -inoutpad IOBUFE O:IO
iopadmap -toutpad IOBUFE O:IO
iopadmap -tinoutpad IOBUFE O:IO
tee -o result.log dump
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
read_verilog ../top.v
synth -top top
muxcover -dmux=3
tee -o result.log dump
write_verilog synth.v
read_verilog ../top.v
synth -top top
muxcover -mux2=336
tee -o result.log dump
write_verilog synth.v
read_verilog ../top.v
prep
simplemap
synth
write_verilog synth.v
read_verilog ../top.v
synth
splice
simplemap top
synth
write_verilog synth.v
read_verilog ../top.v
prep
dff2dffe
simplemap top
synth
write_verilog synth.v
read_verilog ../top.v
proc
techmap
synth
write_verilog synth.v
read_verilog ../top.v
proc
dff2dffe
techmap -assert -map +/techmap.v +/simlib.v
synth
write_verilog synth.v
read_verilog ../top.v
techmap -autoproc
write_verilog synth.v
read_verilog ../top.v
proc
techmap -D U
synth
write_verilog synth.v
read_verilog ../top.v
proc
techmap -extern
synth
write_verilog synth.v
read_verilog ../top.v
proc
techmap -I techmap
synth
write_verilog synth.v
read_verilog ../top.v
proc
techmap -map +/techmap.v
synth
write_verilog synth.v
read_verilog ../top.v
proc
techmap -max_iter 2
synth
write_verilog synth.v
read_verilog ../top.v
proc
techmap -recursive
synth
write_verilog synth.v
read_verilog ../top.v
techmap -wb
write_verilog synth.v
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input [0:0] rst;
input [0:0] a;
wire rst_or;
assign rst_or = |rst;
`ifndef BUG
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
`else
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 1'bZ;
i = 0;
end
2'b01: begin
x = 1'bZ;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 1'bZ;
i = 0;
end
endcase
end
end
`endif
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk)
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk)
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
(* \\keep_hierarchy *) module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
(* \\techmap_simplemap *)module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
(* \\techmap_maccmap *)module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
(* \\top *)module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
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