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yosys-tests
Commit 9c8c9592 by SergeyDegtyar
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Review 'simple' test group

parent c0b775eb
Showing with 1687 additions and 0 deletions
simple_reviewed/.gitignore 0 → 100644
*/work_*/
/.stamp
/run-test.mk
simple_reviewed/Makefile 0 → 100644
PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
all::
run-test.mk: ../generate.py
@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
include run-test.mk
.PHONY: all clean
simple_reviewed/aigmap/aigmap.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap
tee -o result.out dump
proc
aigmap
synth -top top
aigmap
simple_reviewed/aigmap/aigmap_nand.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap -nand
tee -o result.out dump
proc
aigmap -nand
synth -top top
aigmap -nand
simple_reviewed/aigmap/aigmap_select.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap -select
tee -o result.out dump
proc
aigmap -select
synth -top top
simple_reviewed/aigmap/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
reg Y;
wire[3:0] S;
wire[15:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
8 : Y = D[8];
9 : Y = D[9];
10 : Y = D[10];
11 : Y = D[11];
12 : Y = D[12];
13 : Y = D[13];
14 : Y = D[14];
15 : Y = D[15];
endcase
end
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
simple_reviewed/alu/gates.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -g gates
stat
select -assert-count 98 t:$_ANDNOT_
select -assert-count 465 t:$_AND_
select -assert-count 32 t:$_DFF_P_
select -assert-count 786 t:$_NAND_
select -assert-count 43 t:$_NOR_
select -assert-count 3 t:$_NOT_
select -assert-count 92 t:$_ORNOT_
select -assert-count 257 t:$_OR_
select -assert-count 18 t:$_XNOR_
select -assert-count 26 t:$_XOR_
simple_reviewed/alu/luts.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
stat
select -assert-count 32 t:$_DFF_P_
select -assert-count 689 t:$lut
simple_reviewed/alu/top.v 0 → 100644
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule
simple_reviewed/async2sync/async2sync.ys 0 → 100644
read_verilog ../top.v
proc
select -assert-count 2 t:$dffsr
async2sync
select -assert-none t:$dffsr
simple_reviewed/async2sync/async2sync_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
select -assert-count 4 t:$dlatch
async2sync
select -assert-none t:$dlatch
simple_reviewed/async2sync/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/async2sync/top_latch.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple_reviewed/attrmap/attrmap.ys 0 → 100644
read_verilog ../top.v
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
proc
tee -o result1.out dump
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
tee -o result.out dump
simple_reviewed/attrmap/attrmap_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
attrmap -tocase keep -remove keep="true"
tee -o result.out dump
simple_reviewed/attrmap/attrmap_modattr.ys 0 → 100644
read_verilog ../top.v
proc
attrmap -modattr -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 -rename keep keep_attr
tee -o result.out dump
simple_reviewed/attrmap/top.v 0 → 100644
module top (en, a, b);
input en;
input a;
output reg b;
(* keep = "true" *) wire int_dat;
always @(en or a)
b <= (en)? a : 1'bZ;
endmodule
simple_reviewed/clk2fflogic/clk2fflogic.ys 0 → 100644
read_verilog ../top.v
proc
select -assert-any t:$dffsr
select -assert-any t:$dff
select -assert-any t:$adff
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dffsr
select -assert-none t:$dff
select -assert-none t:$adff
select -assert-any t:$ff
simple_reviewed/clk2fflogic/clk2fflogic_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
select -assert-any t:$dlatch
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dlatch
select -assert-any t:$ff
simple_reviewed/clk2fflogic/clk2fflogic_mem.ys 0 → 100644
read_verilog ../top_mem.v
memory_collect
proc
select -assert-any t:$dff
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dff
select -assert-any t:$ff
simple_reviewed/clk2fflogic/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/clk2fflogic/top_latch.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple_reviewed/clk2fflogic/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/design_import/design_import.ys 0 → 100644
read_verilog ../top.v
proc
design -save top
design -import top
write_verilog synth.v
simple_reviewed/design_import/design_import_as.ys 0 → 100644
read_verilog ../top.v
proc
design -save top
design -import top -as top_new
write_verilog synth.v
simple_reviewed/design_import/top.v 0 → 100644
module top
(
input [7:0] x,
output o_and,
output o_or,
output o_xor,
output o_nand,
output o_nor,
output o_xnor
);
assign o_and = &x;
assign o_or = |x;
assign o_xor = ^x;
assign o_nand = ~&x;
assign o_nor = ~|x;
assign o_xnor = ~^x;
endmodule
simple_reviewed/dff2dffe/dff2dffe_error_fail.pat 0 → 100644
ERROR: No cell types matched pattern '$ff'.
simple_reviewed/dff2dffe/dff2dffe_error_fail.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe -direct-match $ff
simple_reviewed/dff2dffe/dff2dffe_unmap.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
tee -o result.log dump
synth -top top
dff2dffe
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
tee -o result.log dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct_match.ys 0 → 100644
read_verilog ../top.v
proc
synth -top top
dff2dffe -direct-match $_DFF_P_
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_mince.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
tee -o result.log dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/dff2dffs/dff2dffs.ys 0 → 100644
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs
select -assert-none t:$_DFF_N_
tee -o result.out stat
simple_reviewed/dff2dffs/dff2dffs_match_init.ys 0 → 100644
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs -match-init
tee -o result.out stat
simple_reviewed/dff2dffs/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffs
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffns
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/dffsr2dff/dffsr2dff.ys 0 → 100644
read_verilog ../top.v
proc
dffsr2dff
techmap
dffsr2dff
design -reset
read_verilog ../top.v
synth -top top
dffsr2dff
flatten
opt
opt_rmdff
dffsr2dff
write_verilog synth.v
simple_reviewed/dffsr2dff/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
.clr (1'b1),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/expose/expose_cut.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -cut
write_verilog synth.v
simple_reviewed/expose/expose_dff.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dff.ys 0 → 100644
read_verilog ../top_dff.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dffr.ys 0 → 100644
read_verilog ../top_dffr.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_evert.ys 0 → 100644
read_verilog ../top.v
expose -evert
synth -top top
expose -evert
proc
expose -evert
flatten
opt
opt_rmdff
expose -evert
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff.ys 0 → 100644
read_verilog ../top.v
proc
expose -evert-dff
synth -top top
expose -evert-dff
proc
flatten
opt
opt_rmdff
expose -evert-dff
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff_shared.ys 0 → 100644
read_verilog ../top.v
proc
expose -evert-dff -shared
synth -top top
proc
flatten
opt
opt_rmdff
expose -evert-dff
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/expose/expose_evert_shared.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -evert -shared
expose -shared -evert
write_verilog synth.v
simple_reviewed/expose/expose_input.ys 0 → 100644
read_verilog ../top.v
synth -top top
expose -input
proc
flatten
opt
opt_rmdff
expose -input
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/expose/expose_sep.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -sep |
write_verilog synth.v
simple_reviewed/expose/expose_shared.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -shared
write_verilog synth.v
simple_reviewed/expose/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/expose/top_dff.v 0 → 100644
module dff
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk (clk),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/expose/top_dffr.v 0 → 100644
module dffr
( input d, clk, rst, output reg q );
always @( posedge clk )
if ( rst )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk (clk),
.rst (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/extract/extract_args_to_perm_fail.pat 0 → 100644
ERROR: Arguments to -perm are not a valid permutation!
simple_reviewed/extract/extract_args_to_perm_fail.ys 0 → 100644
read_verilog ../top.v
extract -map top.v -perm u x u
simple_reviewed/extract/extract_cant_open_output_fail.ys 0 → 100644
read_verilog ../top.v
extract -mine tt/out
simple_reviewed/extract/extract_cell_attr.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -cell_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_compat.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -compat $dff a
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_constports.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -constports
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_param.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -ignore_param $dff param
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_parameters.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -ignore_parameters
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map_and_mine_fail.pat 0 → 100644
ERROR: You cannot mix -map and -mine.
simple_reviewed/extract/extract_map_and_mine_fail.ys 0 → 100644
read_verilog ../top.v
extract -map top.v -mine out.ilang
simple_reviewed/extract/extract_map_design.ys 0 → 100644
read_verilog ../top.v
design -save top_test
extract -map %top_test
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_mine.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang
write_verilog synth.v
simple_reviewed/extract/extract_mine_and_map_fail.pat 0 → 100644
ERROR: You cannot mix -map and -mine.
simple_reviewed/extract/extract_mine_and_map_fail.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -map top.v
simple_reviewed/extract/extract_mine_cells_span.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_cells_span 3 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_limit_matches_per_module.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_limit_matches_per_module 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_max_fanout.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_max_fanout 2
write_verilog synth.v
simple_reviewed/extract/extract_mine_min_freq.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_min_freq 10
write_verilog synth.v
simple_reviewed/extract/extract_mine_split.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_split 2 2
write_verilog synth.v
simple_reviewed/extract/extract_missing_opt_fail.pat 0 → 100644
ERROR: Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.
simple_reviewed/extract/extract_nodefaultswaps.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -nodefaultswaps
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_perm.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -perm $dff D,CLK D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_swap.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -swap $dff D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_verbose.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -verbose
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_wire_attr.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -wire_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/out 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 1
simple_reviewed/extract/top.ilang 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 143
simple_reviewed/extract/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/extract_counter/extract_counter.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_down.ys 0 → 100644
read_verilog ../top_down.v
synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_maxwidth.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter -maxwidth 4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter -pout X
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout_without_args_fail.ys 0 → 100644
read_verilog ../top_err.v
synth_greenpak4
extract_counter -pout
design -reset
read_verilog ../top_err.v
write_verilog synth.v
simple_reviewed/extract_counter/top.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
endmodule
simple_reviewed/extract_counter/top_down.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b11111111;
end else
out <= out - 1;
endmodule
simple_reviewed/extract_counter/top_err.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
//FORCE
endmodule
simple_reviewed/extract_counter/top_negative_reset.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (!reset) begin
out <= 8'b00000000;
end else
out <= out + 1;
endmodule
simple_reviewed/hierarchy/yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v 0 → 100644
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