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yosys-tests
Commit 9af3cae7 by SergeyDegtyar
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Minor fixes

parent ea6ece16
Showing with 19 additions and 41 deletions
backends_reviewed/write_smv/top_fulladder.v
...@@ -7,21 +7,17 @@ module top ...@@ -7,21 +7,17 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends_reviewed/write_xaiger/top.v
...@@ -7,13 +7,13 @@ module top ...@@ -7,13 +7,13 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg ASSERT = 1; reg ASSERT = 1;
(* anyconst *) reg foo; (* anyconst *) reg foo;
(* anyseq *) reg too; (* anyseq *) reg too;
initial begin initial begin
begin begin
A = 0; A = 0;
...@@ -21,23 +21,19 @@ module top ...@@ -21,23 +21,19 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
A <= y + cin + too; A <= y + cin + too;
assume(too); assume(too);
assume(s_eventually too); assume(s_eventually too);
end end
always @(negedge x) begin always @(negedge x) begin
if ($initstate) if ($initstate)
cout <= 0; cout <= 0;
cout <= y + A + foo; cout <= y + A + foo;
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends_reviewed/write_xaiger/top_cant_find_top.v
...@@ -21,7 +21,7 @@ module top ...@@ -21,7 +21,7 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
...@@ -36,9 +36,6 @@ always @(negedge x) begin ...@@ -36,9 +36,6 @@ always @(negedge x) begin
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
......
backends_reviewed/write_xaiger/top_fulladder.v
...@@ -7,21 +7,18 @@ module top ...@@ -7,21 +7,18 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends_reviewed/write_xaiger/top_mem.v
...@@ -7,38 +7,30 @@ module top ...@@ -7,38 +7,30 @@ module top
); );
// Declare the RAM variable // Declare the RAM variable
reg [7:0] ram[63:0]; reg [7:0] ram[63:0];
initial begin initial begin
q_a <= 8'h00; q_a <= 8'h00;
q_b <= 8'd0; q_b <= 8'd0;
end end
// Port A // Port A
always @ (posedge clka) always @ (posedge clka)
begin begin
`ifndef BUG if (we_a)
if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
end end
if (re_b) if (re_b)
begin begin
q_a <= ram[addr_a]; q_a <= ram[addr_a];
end end
end end
// Port B // Port B
always @ (posedge clkb) always @ (posedge clkb)
begin begin
`ifndef BUG if (we_b)
if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
...@@ -48,5 +40,5 @@ module top ...@@ -48,5 +40,5 @@ module top
q_b <= ram[addr_b]; q_b <= ram[addr_b];
end end
end end
endmodule endmodule
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