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lvzhengyang
yosys-tests
Commits
9a201971
Commit
9a201971
authored
Jan 12, 2020
by
Miodrag Milanovic
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Fix regressions
parent
0342cd35
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1 additions
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7 deletions
+1
-7
misc/abc9/abc9_dff_nomfs.ys
+0
-6
simple/alu/luts.ys
+1
-1
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misc/abc9/abc9_dff_nomfs.ys
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100644 → 0
View file @
0342cd35
read_verilog ../top_dff.v
proc
dff2dffe
synth -top top
abc9 -lut 5 -nomfs
abc9 -lut 5
simple/alu/luts.ys
View file @
9a201971
...
@@ -2,4 +2,4 @@ read_verilog ../top.v
...
@@ -2,4 +2,4 @@ read_verilog ../top.v
synth -top top
synth -top top
abc -lut 4
abc -lut 4
select -assert-count 32 t:$_DFF_P_
select -assert-count 32 t:$_DFF_P_
select -assert-count 68
9
t:$lut
select -assert-count 68
8
t:$lut
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