Merge pull request #82 from SergeyDegtyar/review_misc_group

Review misc group

misc/.gitignore

 */work_*/
 /.stamp
+/run-test.mk

misc/scripts/abc_g_simple.ys → misc/abc/abc.ys

@@ -2,4 +2,9 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc -g simple
+abc
+
+select -assert-count 3 t:$_NAND_
+select -assert-count 2 t:$_XOR_
+
+select -assert-none t:$_NAND_ t:$_XOR_ %% t:* %D

misc/scripts/abc9_D.ys → misc/abc/abc_D.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -D 2 -lut 2
+tee -o result.out abc -D 2

misc/abc/abc_cannot_open_fail.pat

+ERROR: Can't open ABC output file

misc/scripts/abc_cannot_open.ys → misc/abc/abc_cannot_open_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log abc -liberty -constr
+tee -o result.out abc -liberty -constr
  abc -liberty -constr

misc/abc/abc_clk_domain_not_found_fail.pat

+ERROR: Clock domain u not found.

misc/scripts/abc_clk_domain_not_found.ys → misc/abc/abc_clk_domain_not_found_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log  abc -dff -clk u
+tee -o result.out  abc -dff -clk u
  abc -dff -clk u

misc/scripts/abc_constr_liberty.ys → misc/abc/abc_constr_liberty.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log  abc -liberty  -constr top.lib
+tee -o result.out  abc -liberty  -constr top.lib

misc/abc/abc_constr_no_liberty_fail.pat

+ERROR: Got -constr but no -liberty!

misc/scripts/abc_constr_no_liberty.ys → misc/abc/abc_constr_no_liberty_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log abc -constr -liberty
+tee -o result.out abc -constr -liberty
 abc -constr -liberty

misc/abc/abc_dff.ys

+read_verilog ../top_dff.v
+synth -top top
+dff2dffe
+tee -o result.log  abc -dff
+ abc -dff

misc/abc/abc_dff_keepff.ys

+read_verilog ../top_dff.v
+synth -top top
+tee -o result.log  abc -keepff
+ abc -dff

misc/abc/abc_div_mul.ys

+read_verilog ../top_div_mul.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc

misc/abc/abc_ffs.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc

misc/abc/abc_ffs_clk.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc -clk clk

misc/abc/abc_fsm.ys

+read_verilog ../top_fsm.v
+synth -top top
+tee -o result.out abc

misc/abc/abc_fsm_all.disable

+read_verilog ../top_fsm.v
+synth -top top
+tee -o result.out abc -g all

misc/abc/abc_fsm_all.ys

+read_verilog ../top_fsm.v
+synth -top top
+tee -o result.out abc -g all

misc/abc/abc_fsm_cmos4.ys

+read_verilog ../top_fsm.v
+synth -top top
+abc -g cmos4
+select -assert-count 6 t:$_AOI3_
+select -assert-count 1 t:$_AOI4_
+select -assert-count 2 t:$_OAI3_

misc/abc/abc_fsm_gates.ys

+read_verilog ../top_fsm.v
+synth -top top
+abc -g gates

misc/abc/abc_g_aig.ys

+read_verilog ../top.v
+synth -top top
+abc -g aig
+select -assert-count 2 t:$_AND_
+select -assert-count 3 t:$_NAND_
+select -assert-count 2 t:$_OR_

misc/abc/abc_g_cmos.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos
+
+select -assert-count 1 t:$_NAND_
+select -assert-count 1 t:$_NOT_
+select -assert-count 1 t:$_OAI3_
+select -assert-count 2 t:$_XNOR_

misc/abc/abc_g_cmos2.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos2
+
+select -assert-count 4 t:$_NAND_
+select -assert-count 5 t:$_NOR_
+select -assert-count 3 t:$_NOT_

misc/abc/abc_g_simple.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc -g simple
+
+select -assert-count 2 t:$_AND_
+select -assert-count 1 t:$_OR_
+select -assert-count 2 t:$_NOT_

misc/scripts/abc_dff.ys → misc/abc/abc_i.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log  abc -dff
+tee -o result.log  abc -I 4
  abc -dff

misc/abc/abc_inv_luts_synt_fail.pat

+ERROR: Invalid -luts syntax.

misc/scripts/abc_inv_luts_synt.ys → misc/abc/abc_inv_luts_synt_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log  abc -luts :
+tee -o result.out  abc -luts :
  abc -liberty -luts :

misc/abc/abc_logic.ys

+read_verilog ../top_logic.v
+proc
+synth -top top
+tee -o result.out abc

misc/abc/abc_logic_loop.ys

+read_verilog ../top_logic_loop.v
+proc
+synth -top top
+tee -o result.out abc

misc/abc/abc_lut.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -lut 4
+ abc -lut 3
+ stat

misc/abc/abc_lut_liberty_fail.pat

+ERROR: Got -lut and -liberty! This two options are exclusive.

misc/scripts/abc_lut_liberty.ys → misc/abc/abc_lut_liberty_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log  abc -lut 2 -liberty top.lib
+tee -o result.out  abc -lut 2 -liberty top.lib
  abc -lut 2 -liberty top.lib

misc/abc/abc_lut_neg.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -lut -4
+ abc -lut -3:1

misc/scripts/abc_g_aig.ys → misc/abc/abc_luts.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log abc -g aig
+tee -o result.log  abc -luts 3:4

misc/abc/abc_markgroups.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc -markgroups

misc/abc/abc_mux.ys

+read_verilog ../top_mux.v
+proc
+synth -top top
+abc
+select -assert-count 139 t:$_MUX_

misc/abc/abc_mux16.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.log abc -mux16
+stat

misc/abc/abc_mux4.ys

+read_verilog ../top_mux.v
+synth -top top
+abc -mux4
+select -assert-count 75 t:$_MUX4_

misc/abc/abc_mux8.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.log abc -mux8
+stat

misc/abc/abc_mux_cmos3.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.out abc -g cmos3
+ abc -g cmos3
+select -assert-count 144 t:$_AOI3_
+select -assert-count 169 t:$_OAI3_

misc/abc/abc_mux_cmos4.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.out abc -g cmos4
+ abc -g cmos4
+
+select -assert-count 111 t:$_AOI3_
+select -assert-count 28  t:$_AOI4_
+select -assert-count 111 t:$_AOI3_
+select -assert-count 24  t:$_OAI4_

misc/scripts/abc9_cant_open_output_file.ys → misc/abc/abc_no_proc.ys

 read_verilog ../top.v
-tee -o result.log abc9 -luts uu
+tee -o result.out abc

misc/scripts/abc9_wo_synth.ys → misc/abc/abc_no_synth.ys

 read_verilog ../top.v
 proc
-tee -o result.log abc9 -lut 2
+tee -o result.out abc

misc/abc/abc_p.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -P 4
+ abc -dff

misc/abc/abc_return_code_fail.pat

+failed: return code 134.

misc/scripts/abc_return_code.ys → misc/abc/abc_return_code_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log abc -g XOR
+tee -o result.out abc -g XOR
 abc -g XOR

misc/abc/abc_script_o_fail.pat

+ERROR: Can't open ABC output file

misc/scripts/abc_script_o.ys → misc/abc/abc_script_o_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log abc -script o
+tee -o result.out abc -script o
 abc -script o

misc/abc/abc_script_top_fail.pat

+ERROR: Can't open ABC output file

misc/abc/abc_script_top_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -script top.yss
+abc -script top.yss

misc/abc/abc_skip_module.ys

+read_verilog ../top_dff.v
+tee -o result.out abc

misc/abc/abc_unsup_gate_type_fail.pat

+ERROR: Command syntax error: Unsupported gate type: XO

misc/scripts/abc_unsup_gate_type.ys → misc/abc/abc_unsup_gate_type_fail.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log abc -g XO
+tee -o result.out abc -g XO
 abc -g XO

misc/abc/top.v

@@ -8,10 +8,6 @@
  output cout
  );
 
-`ifndef BUG
 assign {cout,A} =  cin + y + x;
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule

misc/abc9_dff/top.v → misc/abc/top_dff.v

@@ -5,11 +5,7 @@ module adff
     end
 	always @( posedge clk, posedge clr )
 		if ( clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else
             q <= d;
 endmodule
@@ -21,11 +17,7 @@ module adffn
     end
 	always @( posedge clk, negedge clr )
 		if ( !clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else
             q <= d;
 endmodule
@@ -37,11 +29,7 @@ module dffe
     end
 	always @( posedge clk )
 		if ( en )
-`ifndef BUG        
 			q <= d;
-`else        
-			q <= 1'b0;
-`endif
 endmodule
 
 module dffsr
@@ -51,11 +39,7 @@ module dffsr
     end
 	always @( posedge clk, posedge pre, posedge clr )
 		if ( clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else if ( pre )
 			q <= 1'b1;
 		else
@@ -69,11 +53,7 @@ module ndffnsnr
     end
 	always @( negedge clk, negedge pre, negedge clr )
 		if ( !clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else if ( !pre )
 			q <= 1'b1;
 		else
@@ -95,7 +75,7 @@ dffsr u_dffsr (
         .d (a ),
         .q (b )
     );
-    
+
 ndffnsnr u_ndffnsnr (
         .clk (clk ),
         .clr (clr),
@@ -103,21 +83,21 @@ ndffnsnr u_ndffnsnr (
         .d (a ),
         .q (b1 )
     );
-    
+
 adff u_adff (
         .clk (clk ),
         .clr (clr),
         .d (a ),
         .q (b2 )
     );
-    
+
 adffn u_adffn (
         .clk (clk ),
         .clr (clr),
         .d (a ),
         .q (b3 )
     );
-    
+
 dffe u_dffe (
         .clk (clk ),
         .en (clr),

misc/abc_error/top.v → misc/abc/top_div_mul.v

@@ -8,10 +8,6 @@ module top
  output cout
  );
 
-`ifndef BUG
 assign cout = x / y * cin;
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule

misc/abc/top_fsm.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

misc/abc/top_logic.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1,A2,cout2;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+
+always @(posedge x) begin
+    A2 <=  ~(y | cin);
+end
+always @(posedge x) begin
+    cout2 <= cin ~|y;
+end
+
+endmodule

misc/abc/top_logic_loop.v

+module top
+(
+ input x,
+ input y,
+ input z,
+
+ output A,
+ output B
+ );
+
+ wire A1,B1,A2,B2;
+
+ assign A1 = x & A2;
+ assign A2 = A1 & y;
+ assign A = ~A2;
+
+endmodule

misc/scripts/abc9_W.ys → misc/abc9/abc9_D.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -W -lut 2
+abc9 -D 2 -lut 2

misc/scripts/abc9_fast.ys → misc/abc9/abc9_W.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -fast -lut 2
+abc9 -W -lut 2

misc/abc9/abc9_box.ys

+abc9 -box box.txt -lut 2

misc/abc9/abc9_cant_open_output_file_fail.pat

+ERROR: Can't open ABC output file

misc/scripts/abc9_invalid_luts_syntax.ys → misc/abc9/abc9_cant_open_output_file_fail.ys

 read_verilog ../top.v
-tee -o result.log abc9 -luts 2:2:2:/2
+abc9 -luts uu

misc/abc9/abc9_dff.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+abc9 -lut 5
+abc9 -lut 5

misc/abc9/abc9_dff_nomfs.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+abc9 -lut 5 -nomfs
+abc9 -lut 5

misc/abc9/abc9_dff_techmap.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+techmap
+abc9 -lut 5
+abc9 -lut 5

misc/scripts/abc9_lut.ys → misc/abc9/abc9_fast.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -lut 2
+abc9 -fast -lut 2

misc/abc9/abc9_invalid_luts_syntax_fail.pat

+ERROR: Invalid -luts syntax.

misc/scripts/abc9_wo_proc.ys → misc/abc9/abc9_invalid_luts_syntax_fail.ys

 read_verilog ../top.v
-tee -o result.log abc9 -lut 2
+abc9 -luts 2:2:2:/2

misc/scripts/abc9_luts.ys → misc/abc9/abc9_lut.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -luts 2,3,4
+abc9 -lut 2

misc/scripts/abc9_markgroups.ys → misc/abc9/abc9_luts.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -markgroups -lut 2
+abc9 -luts 2,3,4

misc/scripts/abc9_nocleanup.ys → misc/abc9/abc9_markgroups.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -nocleanup -lut 2
+abc9 -markgroups -lut 2

misc/abc9/abc9_mem.ys

+read_verilog ../top_mem.v
+proc
+dff2dffe
+synth -top top
+abc9 -D 2 -lut 2

misc/abc9/abc9_mux.ys

+read_verilog ../top_mux.v
+proc
+synth -top top
+abc9 -lut 2

misc/scripts/abc9_showtmp.ys → misc/abc9/abc9_nocleanup.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc9 -showtmp -lut 2
+abc9 -nocleanup -lut 2

misc/abc9/abc9_script.ys

+abc9 -script box.txt -lut 2

misc/scripts/abc_D.ys → misc/abc9/abc9_showtmp.ys

@@ -2,4 +2,4 @@ read_verilog ../top.v
 proc
 dff2dffe
 synth -top top
-tee -o result.log abc -D 2
+abc9 -showtmp -lut 2

misc/abc9/abc9_techmap.ys

+read_verilog ../top_mux.v
+proc
+techmap
+abc9 -lut 2

misc/abc9/abc9_wo_proc.ys

+read_verilog ../top_dff.v
+abc9 -lut 2

misc/abc9/abc9_wo_synth.ys

+read_verilog ../top_mux.v
+proc
+abc9 -lut 2

misc/abc9/top.v

@@ -8,10 +8,6 @@
  output cout
  );
 
-`ifndef BUG
 assign {cout,A} =  cin + y + x;
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule

misc/abc_dff/top.v → misc/abc9/top_dff.v

@@ -5,11 +5,7 @@ module adff
     end
 	always @( posedge clk, posedge clr )
 		if ( clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else
             q <= d;
 endmodule
@@ -21,11 +17,7 @@ module adffn
     end
 	always @( posedge clk, negedge clr )
 		if ( !clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else
             q <= d;
 endmodule
@@ -37,11 +29,7 @@ module dffe
     end
 	always @( posedge clk )
 		if ( en )
-`ifndef BUG        
 			q <= d;
-`else        
-			q <= 1'b0;
-`endif
 endmodule
 
 module dffsr
@@ -51,11 +39,7 @@ module dffsr
     end
 	always @( posedge clk, posedge pre, posedge clr )
 		if ( clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else if ( pre )
 			q <= 1'b1;
 		else
@@ -69,11 +53,7 @@ module ndffnsnr
     end
 	always @( negedge clk, negedge pre, negedge clr )
 		if ( !clr )
-`ifndef BUG        
 			q <= 1'b0;
-`else        
-			q <= d;
-`endif
 		else if ( !pre )
 			q <= 1'b1;
 		else
@@ -95,7 +75,7 @@ dffsr u_dffsr (
         .d (a ),
         .q (b )
     );
-    
+
 ndffnsnr u_ndffnsnr (
         .clk (clk ),
         .clr (clr),
@@ -103,21 +83,21 @@ ndffnsnr u_ndffnsnr (
         .d (a ),
         .q (b1 )
     );
-    
+
 adff u_adff (
         .clk (clk ),
         .clr (clr),
         .d (a ),
         .q (b2 )
     );
-    
+
 adffn u_adffn (
         .clk (clk ),
         .clr (clr),
         .d (a ),
         .q (b3 )
     );
-    
+
 dffe u_dffe (
         .clk (clk ),
         .en (clr),

misc/mutate_mem/top.v → misc/abc9/top_mem.v

@@ -7,38 +7,30 @@ module top
 );
 	// Declare the RAM variable
 	reg [7:0] ram[63:0];
-	
+
 	initial begin
-        q_a <= 8'h00;        
+        q_a <= 8'h00;
         q_b <= 8'd0;
 	end
-	
+
 	// Port A
 	always @ (posedge clka)
 	begin
-`ifndef BUG        
-		if (we_a) 
-`else        
-		if (we_b) 
-`endif
+		if (we_a)
 		begin
 			ram[addr_a] <= data_a;
 			q_a <= data_a;
 		end
-		if (re_b) 
+		if (re_b)
 		begin
 			q_a <= ram[addr_a];
 		end
 	end
-	
+
 	// Port B
 	always @ (posedge clkb)
 	begin
-`ifndef BUG        
-		if (we_b) 
-`else        
-		if (we_a) 
-`endif
+		if (we_b)
 		begin
 			ram[addr_b] <= data_b;
 			q_b <= data_b;
@@ -48,5 +40,5 @@ module top
 			q_b <= ram[addr_b];
 		end
 	end
-	
-endmodule								 
+
+endmodule

misc/abc_mux/top.v → misc/abc9/top_mux.v

@@ -3,6 +3,7 @@ input [7:0] S,
 input [255:0] D,
 output M256
 );
+parameter i = 3;
 
 assign M256 = D[S];
 

misc/abc9_error/top.v

-(* black_box *) module top
-(
- input x,
- input y,
- input cin,
-
- output A,
- output cout
- );
-
-`ifndef BUG
-assign {cout,A} =  cin + y + x;
-`else
-assign {cout,A} =  cin - y * x;
-`endif
-
-endmodule

misc/add/add.pat

+wire width 0 \\w

misc/scripts/add.ys → misc/add/add.ys

 read_verilog ../top.v
 add -wire w 0
-tee -o result.log dump
+tee -o result.out dump

misc/add/add_error_fail.pat

+ERROR: Found incompatible object with same name in module \\top2!

misc/add/add_global_input.pat

+wire width 32000 input 6 \\gi

misc/scripts/add_global_input.ys → misc/add/add_global_input.ys

 read_verilog ../top.v
 add -global_input gi 32000
-tee -o result.log dump
+tee -o result.out dump

misc/add/add_inout.pat

+wire width 3 inout 6 \\34

misc/scripts/add_inout.ys → misc/add/add_inout.ys

 read_verilog ../top.v
  add -inout \34 3
-tee -o result.log dump
+tee -o result.out dump

misc/add/add_input.pat

+wire width 2 input 6 \\i