Update testbenches for MACC and FSMs

simple/fsm/testbench.v

@@ -31,21 +31,35 @@ module testbench;
     );
     
     initial begin
-        rst <= 0;
-        #5
         rst <= 1;
         #5
-        a <= 1;
-        b <= 0;
-        #50
+        rst <= 0;
+    end
+	
+	initial begin
 		a <= 0;
+		repeat (20000) #3 a = !a;
+	end
+	
+	initial begin
 		b <= 0;
-        #50
-        a <= 0;
-        b <= 1;
-        #50
-        a <= 1;
-        b <= 1;
+		repeat (20000) #4 b = !b;
 	end
 	
+    assert g0_test(.clk(clk), .A(g0));
+	assert g1_test(.clk(clk), .A(g1));
+  
+endmodule
+
+
+module assert(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ASSERTION FAILED in %m:",$time," ",A);
+            //$finish;
+        end
+    end
 endmodule

simple/fsm_opt/testbench.v

@@ -31,21 +31,35 @@ module testbench;
     );
     
     initial begin
-        rst <= 0;
-        #5
         rst <= 1;
         #5
-        a <= 1;
-        b <= 0;
-        #50
+        rst <= 0;
+    end
+	
+	initial begin
 		a <= 0;
+		repeat (20000) #3 a = !a;
+	end
+	
+	initial begin
 		b <= 0;
-        #50
-        a <= 0;
-        b <= 1;
-        #50
-        a <= 1;
-        b <= 1;
+		repeat (20000) #4 b = !b;
 	end
 	
+    assert g0_test(.clk(clk), .A(g0));
+	assert g1_test(.clk(clk), .A(g1));
+  
+endmodule
+
+
+module assert(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ASSERTION FAILED in %m:",$time," ",A);
+            //$finish;
+        end
+    end
 endmodule

simple/fsm_opt/top.v

@@ -71,7 +71,7 @@ fsm u_fsm ( .clock(clk),
 assign g0 = g[0];
 assign g1 = g[1];
 
-assign a = r[0];
-assign b = r[1];
+assign r[0] = a;
+assign r[1] = b;
 
 endmodule

simple/fsm_unreach/testbench.v

@@ -39,6 +39,8 @@ module testbench;
         #5
         rst <= 1;
         #5
+        rst <= 0;
+        #5
         a <= 4'b1111;
         b <= 4'b1010;        
         c <= 4'b1011;
@@ -56,4 +58,21 @@ module testbench;
         c <= 4'b0000;
     end
     
+    assert x_test(.clk(clk), .A(x));
+	assert y_test(.clk(clk), .A(y));
+	assert z_test(.clk(clk), .A(z));
+  
+endmodule
+
+
+module assert(input clk, input [4:0] A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 4'b0000)
+        begin
+            $display("ASSERTION FAILED in %m:",$time," ",A);
+            //$finish;
+        end
+    end
 endmodule

simple/macc/testbench.v

@@ -19,6 +19,7 @@ module testbench;
     reg [17:0] dinB;
     reg carryin;
     reg rst;
+	wire [47:0] p;
 
     top uut (
         .p (p),
@@ -51,4 +52,25 @@ module testbench;
         carryin <= 0;
     end
 	
+	assert macc_test(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
+  
+endmodule
+
+
+module assert(input clk, input [24:0] A, input [17:0] B, input C, input [47:0] P);
+	reg [47:0] p;
+	always @(posedge clk)
+    begin
+        //#1;
+		@(posedge clk);
+		@(posedge clk);		
+		@(posedge clk);
+		@(posedge clk);
+		assign p = (A * B) + C; 
+        if (P != p)
+        begin
+            $display("ASSERTION FAILED in %m:",$time," ",P," ",p);
+            //$finish;
+        end
+    end
 endmodule