Skip to content

Y
yosys-tests
Unverified Commit 94c60f8a by Miodrag Milanović Committed by GitHub
Options

Merge pull request #31 from SergeyDegtyar/master 

Add checks for certain cell type into 'simple' tests.
parents fc602d68 9ab6e149
Showing with 361 additions and 24 deletions
simple/Makefile
......@@ -57,7 +57,8 @@ $(eval $(call template,full_adder,full_adder half_adder))
$(eval $(call template,reduce,reduce reduce_allow_off_chain))
#nlutmap
$(eval $(call template,nlutmap,nlutmap nlutmap_luts nlutmap_assert))
$(eval $(call template,nlutmap,nlutmap))
$(eval $(call template,nlutmap_opt,nlutmap_luts nlutmap_assert))
#zinit
$(eval $(call template,zinit,zinit zinit_singleton))
......@@ -68,13 +69,14 @@ $(eval $(call template,clk2fflogic_latch,clk2fflogic))
$(eval $(call template,clk2fflogic_mem,clk2fflogic_mem))
#muxcover
$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux8 muxcover_mux8_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode))
$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode))
$(eval $(call template,muxcover_mux8,muxcover_mux8 muxcover_mux8_nodecode))
#aigmap
$(eval $(call template,aigmap,aigmap aigmap_nand))
#memory_memx, memory_nordff(75-101 not covered), memory_unpack(91-108 not covered)
$(eval $(call template,memory,memory_memx memory_nordff memory_unpack memory_nomap memory_nordff_opt memory_memx_opt memory_bram_opt memory_share))
$(eval $(call template,memory,memory memory_memx memory_nordff memory_unpack memory_nomap memory_nordff_opt memory_memx_opt memory_bram_opt memory_share))
#uniquify
$(eval $(call template,uniquify,uniquify))
......@@ -122,7 +124,8 @@ $(eval $(call template,flowmap_mem,flowmap flowmap_cells flowmap_debug_relax flo
$(eval $(call template,iopadmap,iopadmap))
#tribuf
$(eval $(call template,tribuf,tribuf tribuf_top tribuf_merge_top tribuf_logic_top tribuf_merge_logic_top))
$(eval $(call template,tribuf,tribuf tribuf_top tribuf_merge_top))
$(eval $(call template,tribuf_logic,tribuf_logic_top tribuf_merge_logic_top))
#expose
$(eval $(call template,expose,expose_cut expose_input expose_evert expose_sep expose_shared expose_dff expose_evert_dff expose_evert_shared expose_evert_dff_shared))
......
simple/muxcover_mux8/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] D = 1;
reg [5:0] S = 0;
wire M256;
top uut (
.S (S ),
.D (D ),
.M256 (M256 )
);
always @(posedge clk) begin
//#3;
D <= {D[62:0],D[63]};
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(M256));
endmodule
simple/muxcover_mux8/top.v 0 → 100644
module top (
input [5:0] S,
input [63:0] D,
output M256
);
`ifndef BUG
assign M256 = D[S];
`else
assign M256 = S[D];
`endif
endmodule
simple/nlutmap_opt/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
simple/nlutmap_opt/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire p,r,s;
xor (p,x,y);
`ifndef BUG
xor (A,p,cin);
`else
and (A,p,cin);
`endif
and(r,p,cin);
and(s,x,y);
or(cout,r,s);
endmodule
simple/run.sh
......@@ -57,11 +57,101 @@ if [ "$2" = "falsify" ]; then
echo PASS > ${1}_${2}.status
fi
else
#cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
cell_failed="0"
if test -f "result.log"; then
expected_string=""
expected="1"
if [ "$1" = "aigmap" ]; then
expected_string="\$mux"
expected="0"
elif [ "$1" = "async2sync" ] ||\
[ "$1" = "clk2fflogic" ] ||\
[ "$1" = "clk2fflogic_latch" ] ||\
[ "$1" = "clk2fflogic_mem" ]; then
expected_string="\$adff"
expected="0"
elif [ "$1" = "dff2dffe_unmap" ]; then
expected_string="\$dffe"
expected="0"
elif [ "$1" = "flowmap" ] ||\
[ "$1" = "flowmap_latch" ] ||\
[ "$1" = "flowmap_mem" ]; then
expected_string="cell \$lut \$auto\$flowmap"
elif [ "$1" = "fsm" ] ||\
[ "$1" = "fsm_expand" ] ||\
[ "$1" = "fsm_export" ] ||\
[ "$1" = "fsm_opt" ] ||\
[ "$1" = "fsm_recode" ] ||\
[ "$1" = "fsm_unreach" ]; then
expected_string="cell \$fsm"
elif [ "$1" = "full_adder" ]; then
expected_string="\$fa"
elif [ "$1" = "ice40_dsp_mult" ] ||\
[ "$1" = "ice40_dsp_mult_acc" ]; then
expected_string="SB_MAC16"
elif [ "$1" = "ice40_dsp_mult_a_larger" ] ||\
[ "$1" = "ice40_dsp_mult_b_larger" ] ||\
[ "$1" = "ice40_dsp_mult_out_larger" ] ||\
[ "$1" = "ice40_dsp_mult_signed" ]; then
expected_string="\$mul"
elif [ "$1" = "inout_port_demote" ]; then
expected_string="inout"
expected="0"
elif [ "$1" = "iopadmap" ]; then
expected_string="IBUF \$auto\$iopadmap"
elif [ "$1" = "macc" ]; then
expected_string="cell \$macc"
expected="0"
elif [ "$1" = "memory" ]; then
expected_string="cell \$mem "
expected="0"
elif [ "$1" = "muxcover" ] ||\
[ "$1" = "muxcover_mux8" ]; then
expected_string="\$_MUX_"
expected="0"
elif [ "$1" = "nlutmap" ]; then
expected_string="\$lut"
expected="0"
elif [ "$1" = "nlutmap_opt" ]; then
expected_string="\$lut"
elif [ "$1" = "opt_demorgan_reduce" ]; then
expected_string="cell \$not \$auto\$opt_demorgan"
elif [ "$1" = "reduce" ]; then
expected_string="cell \$reduce_"
elif [ "$1" = "tribuf" ]; then
expected_string="cell \$tribuf"
elif [ "$1" = "tribuf_logic" ]; then
expected_string="cell \$tribuf"
expected="0"
elif [ "$1" = "zinit" ]; then
expected_string="cell \$_NOT_ \$auto\$zinit"
fi
if test -f "result.log"; then
if grep "$expected_string" result.log; then
if [ $expected = "1" ]; then
cell_failed="0"
else
cell_failed="1"
fi
else
if [ $expected = "1" ]; then
cell_failed="1"
else
cell_failed="0"
fi
fi
fi
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
elif [ $cell_failed = '1' ]; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
......
simple/scripts/aigmap.ys
read_verilog ../top.v
aigmap
tee -o result.log dump
proc
aigmap
synth -top top
......
simple/scripts/aigmap_nand.ys
read_verilog ../top.v
aigmap -nand
tee -o result.log dump
proc
aigmap -nand
synth -top top
......
simple/scripts/async2sync.ys
read_verilog ../top.v
proc
async2sync
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/clk2fflogic.ys
read_verilog ../top.v
proc
clk2fflogic
tee -o result.log dump
synth -top top
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
write_verilog synth.v
simple/scripts/clk2fflogic_mem.ys
......@@ -2,8 +2,9 @@ read_verilog ../top.v
memory_collect
proc
clk2fflogic
tee -o result.log dump
synth -top top
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
write_verilog synth.v
simple/scripts/deminout.ys
read_verilog ../top.v
deminout
tee -o result.log dump
write_verilog synth.v
simple/scripts/dff2dffe_unmap.ys
......@@ -2,6 +2,7 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
tee -o result.log dump
synth -top top
dff2dffe
dff2dffe -unmap
......
simple/scripts/dff2dffe_unmap_direct.ys
......@@ -3,6 +3,7 @@ proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
tee -o result.log dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
......
simple/scripts/dff2dffe_unmap_mince.ys
......@@ -2,6 +2,7 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
tee -o result.log dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
......
simple/scripts/flowmap.ys
read_verilog ../top.v
synth -top top
flowmap
tee -o result.log dump
write_verilog synth.v
simple/scripts/fsm.ys
......@@ -4,5 +4,6 @@ fsm_detect
fsm_extract
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_command.ys
read_verilog ../top.v
proc
fsm
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_command_expand.ys
read_verilog ../top.v
proc
fsm -expand
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_command_export.ys
read_verilog ../top.v
proc
fsm -export
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encfile.ys
read_verilog ../top.v
proc
fsm -encfile fsm.fsm
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encoding_auto.ys
......@@ -7,5 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding auto
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encoding_binary.ys
read_verilog ../top.v
proc
fsm -encoding binary
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encoding_none.ys
......@@ -7,5 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding none
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encoding_one-hot.ys
read_verilog ../top.v
proc
fsm -encoding one-hot
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encoding_unknown.ys
......@@ -7,5 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding unknown
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_encoding_user.ys
......@@ -7,5 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding user
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_expand.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_expand
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_expand_all.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_expand -full
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_expand_full.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_expand -full
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_export.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_export
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_export_noauto.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_export -noauto
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_export_o.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_export -o fsm.kiss2
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_export_origenc.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_export -origenc
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_fm_set_fsm_file.ys
read_verilog ../top.v
proc
fsm -fm_set_fsm_file file.file
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_fullexpand.ys
read_verilog ../top.v
proc
fsm -fullexpand
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_map_binary_encoding.ys
......@@ -6,5 +6,6 @@ fsm_recode -encoding binary
fsm_map
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_nodetect.ys
read_verilog ../top.v
proc
fsm -nodetect
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_nomap.ys
read_verilog ../top.v
proc
fsm -nomap
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_norecode.ys
read_verilog ../top.v
proc
fsm -norecode
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_recode
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_all_opt.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_recode -encoding binary -fm_set_fsm_file file.file -encfile file.fsm
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_encfile.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_recode -encfile file.fsm
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_encoding_binary.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_recode -encoding binary
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_encoding_binary_twice.ys
......@@ -6,5 +6,6 @@ fsm_recode -encoding binary
fsm_recode -encoding binary
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_encoding_one_hot.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_recode -encoding one-hot
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_fm_set_fsm_file.ys
......@@ -5,5 +5,6 @@ fsm_extract
fsm_recode -fm_set_fsm_file file.file
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/full_adder.ys
read_verilog ../top.v
synth -top top
extract_fa -fa -v
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/half_adder.ys
......@@ -2,5 +2,6 @@ read_verilog ../top.v
proc
synth -top top
extract_fa -ha -v
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/ice40_dsp.ys
read_verilog ../top.v
proc
ice40_dsp
tee -o result.log dump
synth_ice40 -top top
design -reset
read_verilog ../top.v
......
simple/scripts/iopadmap.ys
......@@ -2,6 +2,7 @@ read_verilog ../top.v
proc
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
tee -o result.log dump
design -reset
read_verilog ../top.v
proc
......
simple/scripts/macc.ys
read_verilog ../top.v
read_verilog ../top.v
proc
alumacc
maccmap -unmap
maccmap -unmap
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/memory.ys
read_verilog ../top.v
proc
memory
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_bram_opt.ys
read_verilog ../top.v
proc
memory -bram ../words.v
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_memx.ys
read_verilog ../top.v
proc
memory_memx
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_memx_opt.ys
read_verilog ../top.v
proc
memory -memx
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_nomap.ys
read_verilog ../top.v
proc
memory -nomap
memory_map
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_nordff.ys
read_verilog ../top.v
proc
memory_collect
memory_nordff
memory_dff
opt_clean
memory_share
opt_clean
memory_collect
memory_map
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_nordff_opt.ys
read_verilog ../top.v
proc
memory -nordff
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_share.ys
......@@ -3,6 +3,7 @@ proc
memory_share
memory
memory_share
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/memory_unpack.ys
......@@ -3,6 +3,7 @@ proc
memory_collect
memory_memx
memory_unpack
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
......
simple/scripts/mux.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
muxcover
write_verilog synth.v
simple/scripts/muxcover.ys
read_verilog ../top.v
synth -top top
muxcover
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_4_8_16_nodecode.ys
read_verilog ../top.v
synth -top top
muxcover -mux4 -mux8 -mux16 -nodecode
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_mux16.ys
read_verilog ../top.v
synth -top top
muxcover -mux16
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_mux16_nodecode.ys
read_verilog ../top.v
synth -top top
muxcover -mux16 -nodecode
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_mux4.ys
read_verilog ../top.v
synth -top top
muxcover -mux4
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_mux4_nodecode.ys
read_verilog ../top.v
synth -top top
muxcover -mux4 -nodecode
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_mux8.ys
read_verilog ../top.v
synth -top top
muxcover -mux8
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_mux8_nodecode.ys
read_verilog ../top.v
synth -top top
muxcover -mux8 -nodecode
tee -o result.log dump
write_verilog synth.v
simple/scripts/muxcover_nodecode.ys
read_verilog ../top.v
synth -top top
muxcover -nodecode
tee -o result.log dump
write_verilog synth.v
simple/scripts/nlutmap.ys
......@@ -2,4 +2,5 @@ read_verilog ../top.v
synth -top top
abc -lut 2:5
nlutmap
tee -o result.log dump
write_verilog synth.v
simple/scripts/nlutmap_assert.ys
......@@ -2,4 +2,5 @@ read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40 -assert
tee -o result.log dump
write_verilog synth.v
simple/scripts/nlutmap_luts.ys
......@@ -2,4 +2,5 @@ read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40
tee -o result.log dump
write_verilog synth.v
simple/scripts/opt_demorgan.ys
......@@ -2,4 +2,5 @@ read_verilog ../top.v
techmap -autoproc
extract_reduce
opt_demorgan top
tee -o result.log dump
write_verilog synth.v
simple/scripts/reduce.ys
read_verilog ../top.v
synth -top top
extract_reduce
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/reduce_allow_off_chain.ys
read_verilog ../top.v
synth -top top
extract_reduce -allow-off-chain
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/tribuf.ys
......@@ -3,6 +3,7 @@ tribuf
tribuf
proc
tribuf
tee -o result.log dump
synth -top top
tribuf
write_verilog synth.v
simple/scripts/tribuf_logic_top.ys
read_verilog ../top.v
tribuf -logic top
tribuf -logic tristate
synth -top top
tribuf -logic top
tribuf -logic tristate
tee -o result.log dump
write_verilog synth.v
simple/scripts/tribuf_merge_logic_top.ys
read_verilog ../top.v
tribuf -logic top
tribuf -merge top
tribuf -logic tristate
tribuf -merge tristate
synth -top top
tribuf -merge -logic top
tribuf -merge -logic tristate
tee -o result.log dump
write_verilog synth.v
simple/scripts/tribuf_merge_top.ys
read_verilog ../top.v
tribuf -merge top
tribuf -merge tristate
tee -o result.log dump
synth -top top
tribuf -merge top
tribuf -merge tristate
write_verilog synth.v
simple/scripts/tribuf_top.ys
read_verilog ../top.v
proc
tribuf top
tribuf tristate
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/zinit.ys
read_verilog ../top.v
synth -top top
zinit
write_verilog synth.v
tee -o result.log dump
write_verilog synth.v
simple/scripts/zinit_singleton.ys
read_verilog ../top.v
synth -top top
zinit -singleton
write_verilog synth.v
zinit -all
tee -o result.log dump
write_verilog synth.v
simple/tribuf_logic/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.en (en ),
.a (dinA ),
.b (doutB )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_tri b_test(.en(en), .A(dinA), .B(doutB));
endmodule
simple/tribuf_logic/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
`ifndef BUG
always @(en or i)
o <= (en)? i : 1'bZ;
`else
always @(en or i)
o <= (en)? ~i : 1'bZ;
`endif
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment