Fix tests counters

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys

@@ -16,14 +16,14 @@ cd asym_ram_tdp_write_first
 stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
-select -assert-count 200 t:FDRE
-select -assert-count 27 t:LUT1
-select -assert-count 23 t:LUT2
-select -assert-count 48 t:LUT3
-select -assert-count 24 t:LUT4
-select -assert-count 138 t:LUT5
-select -assert-count 227 t:LUT6
-select -assert-count 318 t:MUXF7
-select -assert-count 142 t:MUXF8
+select -assert-count 136 t:FDRE
+select -assert-count 13 t:LUT1
+select -assert-count 12 t:LUT2
+select -assert-count 44 t:LUT3
+select -assert-count 9 t:LUT4
+select -assert-count 68 t:LUT5
+select -assert-count 165 t:LUT6
+select -assert-count 190 t:MUXF7
+select -assert-count 76 t:MUXF8
 
 select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys

@@ -18,8 +18,9 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 1 t:DSP48E1
-select -assert-count 16 t:LUT2
 select -assert-count 9 t:LUT3
+select -assert-count 9 t:LUT4
 select -assert-count 6 t:CARRY4
+select -assert-count 8 t:INV
 
-select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:CARRY4 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT4 t:LUT3 t:CARRY4 t:INV %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys

@@ -16,10 +16,11 @@ cd xilinx_ultraram_single_port_no_change
 stat
 #Vivado synthesizes 1 RAMB36E1, 28 FDRE.
 select -assert-count 1 t:BUFG
-select -assert-count 53 t:FDRE
-select -assert-count 2 t:LUT2
+select -assert-count 60 t:FDRE
+select -assert-count 1 t:LUT2
 select -assert-count 10 t:LUT3
-select -assert-count 1 t:LUT4
+select -assert-count 24 t:LUT4
 select -assert-count 16 t:RAM128X1D
+select -assert-count 8 t:INV
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D t:INV %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys

@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 
 design -load postopt
 cd xilinx_ultraram_single_port_read_first
+stat
 #Vivado synthesizes 1 RAMB18E1, 28 FDRE.
 select -assert-count 1 t:BUFG
-select -assert-count 53 t:FDRE
-select -assert-count 1 t:INV
+select -assert-count 60 t:FDRE
 select -assert-count 1 t:LUT2
-select -assert-count 10 t:LUT3
+select -assert-count 34 t:LUT3
 select -assert-count 16 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D

simple/opt/opt_clkinv.ys → simple/opt/opt_noclkinv.ys

@@ -2,7 +2,7 @@ read_verilog ../top.v
 proc
 fsm_detect
 fsm_extract
-opt -clkinv
+opt -noclkinv
 select -assert-count 1 t:$dff
 select -assert-count 1 t:$fsm
 select -assert-count 8 t:$mux