Commit 90d53f26 by Miodrag Milanovic

Fix tests counters

parent 40bcbe83
...@@ -16,14 +16,14 @@ cd asym_ram_tdp_write_first ...@@ -16,14 +16,14 @@ cd asym_ram_tdp_write_first
stat stat
#Vivado synthesizes 1 RAMB18E1. #Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG select -assert-count 2 t:BUFG
select -assert-count 200 t:FDRE select -assert-count 136 t:FDRE
select -assert-count 27 t:LUT1 select -assert-count 13 t:LUT1
select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT2
select -assert-count 48 t:LUT3 select -assert-count 44 t:LUT3
select -assert-count 24 t:LUT4 select -assert-count 9 t:LUT4
select -assert-count 138 t:LUT5 select -assert-count 68 t:LUT5
select -assert-count 227 t:LUT6 select -assert-count 165 t:LUT6
select -assert-count 318 t:MUXF7 select -assert-count 190 t:MUXF7
select -assert-count 142 t:MUXF8 select -assert-count 76 t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
...@@ -18,8 +18,9 @@ stat ...@@ -18,8 +18,9 @@ stat
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE select -assert-count 16 t:FDRE
select -assert-count 1 t:DSP48E1 select -assert-count 1 t:DSP48E1
select -assert-count 16 t:LUT2
select -assert-count 9 t:LUT3 select -assert-count 9 t:LUT3
select -assert-count 9 t:LUT4
select -assert-count 6 t:CARRY4 select -assert-count 6 t:CARRY4
select -assert-count 8 t:INV
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:CARRY4 %% t:* %D select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT4 t:LUT3 t:CARRY4 t:INV %% t:* %D
...@@ -16,10 +16,11 @@ cd xilinx_ultraram_single_port_no_change ...@@ -16,10 +16,11 @@ cd xilinx_ultraram_single_port_no_change
stat stat
#Vivado synthesizes 1 RAMB36E1, 28 FDRE. #Vivado synthesizes 1 RAMB36E1, 28 FDRE.
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE select -assert-count 60 t:FDRE
select -assert-count 2 t:LUT2 select -assert-count 1 t:LUT2
select -assert-count 10 t:LUT3 select -assert-count 10 t:LUT3
select -assert-count 1 t:LUT4 select -assert-count 24 t:LUT4
select -assert-count 16 t:RAM128X1D select -assert-count 16 t:RAM128X1D
select -assert-count 8 t:INV
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D %% t:* %D select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D t:INV %% t:* %D
...@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter ...@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
design -load postopt design -load postopt
cd xilinx_ultraram_single_port_read_first cd xilinx_ultraram_single_port_read_first
stat
#Vivado synthesizes 1 RAMB18E1, 28 FDRE. #Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE select -assert-count 60 t:FDRE
select -assert-count 1 t:INV
select -assert-count 1 t:LUT2 select -assert-count 1 t:LUT2
select -assert-count 10 t:LUT3 select -assert-count 34 t:LUT3
select -assert-count 16 t:RAM128X1D select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
...@@ -2,7 +2,7 @@ read_verilog ../top.v ...@@ -2,7 +2,7 @@ read_verilog ../top.v
proc proc
fsm_detect fsm_detect
fsm_extract fsm_extract
opt -clkinv opt -noclkinv
select -assert-count 1 t:$dff select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux select -assert-count 8 t:$mux
......
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