Add checks for certain cell type into 'misc' tests.

Testing problems:

1.scc_feedback - Feedback is detected not in each case(with different
options).
2.splice/splice_port - No any changes in the dump after splice -port
command.
3.test_cell/test_cell_macc - ERROR: Assert `port_declared == true'
failed in kernel/rtlil.cc:1352.

misc/delete/top.v

@@ -24,10 +24,10 @@ endmodule
 
 module middle
 (
-	input x,
+	input ux,
 	input y,
 	output o
 );
 
-assign o = x + y;
+assign o = ux + y;
 endmodule

misc/run.sh

@@ -17,8 +17,180 @@ if [ $? != 0 ] ; then
     exit 0
 fi
 
+
+#cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
+cell_failed="0"
+expected_string=""
+expected="1"
+
+if   [ "$2" = "add" ]; then
+	expected_string="wire width 0 \\\w"
+elif [ "$2" = "add_global_input" ]; then
+	expected_string="wire width 32000 input 6 \\\gi"
+elif [ "$2" = "add_input" ]; then
+	expected_string="wire width 2 input 6 \\\i"
+elif [ "$2" = "add_output" ]; then
+	expected_string="wire width 3 output 6 \\\o"
+elif [ "$2" = "add_inout" ]; then
+	expected_string="wire width 3 inout 6 \\\34"
+elif [ "$2" = "add_wire" ]; then
+	expected_string="wire \\\w"
+elif [ "$2" = "assertpmux" ]; then
+	expected_string="cell \$assert"
+elif [ "$2" = "assertpmux_always" ]; then
+	expected_string="cell \$assert"
+elif [ "$2" = "assertpmux_noinit" ]; then
+	expected_string="cell \$assert"
+elif [ "$1" = "blackbox" ]; then
+	expected_string="attribute \\\blackbox 1"
+elif [ "$2" = "chformal" ]; then
+	expected_string="cell \$assert"
+	expected="0"
+elif [ "$2" = "chformal_assert" ]; then
+	expected_string="cell \$assert"
+	expected="0"
+elif [ "$2" = "chformal_assert2assume" ]; then
+	expected_string="cell \$assert"
+	expected="0"
+elif [ "$2" = "chformal_assume" ]; then
+	expected_string="cell \$assume"
+	expected="0"
+elif [ "$2" = "chformal_assume2assert" ]; then
+	expected_string="cell \$assume"
+	expected="0"
+elif [ "$2" = "chformal_fair" ]; then
+	expected_string="cell \$fair"
+	expected="0"
+elif [ "$2" = "chformal_fair2live" ]; then
+	expected_string="cell \$fair"
+	expected="0"
+elif [ "$2" = "chformal_fair2live_assert2assume" ]; then
+	expected_string="cell \$fair"
+	expected="0"
+elif [ "$2" = "chformal_live" ]; then
+	expected_string="cell \$live"
+	expected="0"
+elif [ "$2" = "chformal_live2fair" ]; then
+	expected_string="cell \$live"
+	expected="0"
+elif [ "$2" = "delete" ]; then
+	expected_string="module \\\middle"
+	expected="0"
+elif [ "$2" = "delete_proc" ]; then
+	expected_string="process \$proc\$../top.v:13\$1"
+	expected="0"
+elif [ "$2" = "delete_input" ]; then
+	expected_string="wire input 1 \\\x"
+	expected="0"
+elif [ "$2" = "delete_output" ]; then
+	expected_string="wire output 3 \\\o"
+	expected="0"
+elif [ "$2" = "delete_port" ]; then
+	expected_string="wire output 4 \\\A"
+	expected="0"
+elif [ "$2" = "delete_cell" ]; then
+	expected_string="cell \$mux \$ternary\$../top.v:16\$2"
+	expected="0"
+elif [ "$2" = "delete_wire" ]; then
+	expected_string="wire \\\o"
+	expected="0"
+elif [ "$2" = "delete_mem" ]; then
+	expected_string="cell \$memrd \$memrd\$\ram\$../top.v:30\$7"
+	expected="0"
+elif [ "$2" = "edgetypes" ]; then
+	expected_string="\$add"
+elif [ "$1" = "fmcombine" ]; then
+	expected_string="Combining cells "
+elif [ "$1" = "insbuf" ]; then
+	expected_string="cell \$_BUF_ \$auto\$insbuf"
+elif [ "$1" = "ltp" ]; then
+	expected_string="Longest topological path in"
+elif [ "$1" = "mutate" ]; then
+	if [ "$2" = "mutate_all" ] || \
+	   [ "$2" = "mutate_cnot0" ] || \
+	   [ "$2" = "mutate_cnot1" ] || \
+	   [ "$2" = "mutate_const0" ] || \
+	   [ "$2" = "mutate_const1" ] || \
+	   [ "$2" = "mutate_inv" ]; then
+	expected_string="\$auto\$mutate"
+	fi
+elif [ "$1" = "mutate_mem" ]; then
+	if [ "$2" = "mutate_all" ]; then
+	expected_string="\$auto\$mutate"
+	fi
+elif [ "$2" = "pmuxtree" ]; then
+	expected_string="cell \$pmux"
+	expected="0"
+elif [ "$1" = "qwp" ]; then
+	expected_string="attribute \\\qwp_position"
+elif [ "$2" = "rename" ]; then
+	expected_string="module \\\mid_module"
+elif [ "$2" = "rename_low" ]; then
+	expected_string="module \\\newlow"
+elif [ "$2" = "rename_top" ]; then
+	expected_string="module \\\new_top"
+elif [ "$2" = "rmports" ]; then
+	expected_string="wire output 5 \\\cout"
+	expected="0"
+elif [ "$2" = "scatter" ]; then
+	expected_string="\$auto\$scatter"
+elif [ "$1" = "scc" ] || \
+	 [ "$1" = "scc_hier_feedback" ]; then
+	expected_string="0 SCCs"
+elif [ "$1" = "scc_feedback" ]; then
+	expected_string="0 SCCs"
+	expected="0"
+elif [ "$1" = "setattr" ] || \
+	 [ "$1" = "setattr_mem" ]; then
+	if [ "$2" = "setattr" ] || \
+	   [ "$2" = "setattr_top" ] || \
+	   [ "$2" = "setattr_unset" ]; then
+	expected_string="attribute \\\u 1"
+	expected="0"
+	else
+	expected_string="attribute \\\u 1"
+	fi
+elif [ "$1" = "sim" ] || \
+	 [ "$1" = "sim_mem" ]; then
+	if [ "$2" != "sim_d" ]; then
+	expected_string="Simulating cycle"
+	fi
+elif [ "$1" = "splice" ]; then
+	expected_string="\$auto\$splice"
+elif [ "$1" = "splitnets" ]; then
+	if [ "$2" = "splitnets_dpf" ] || \
+	   [ "$2" = "splitnets_driver" ]; then
+	expected_string="wire width 8 \$memwr"
+	else
+	expected_string="wire width 8 \$memwr"
+	expected="0"
+	fi
+elif [ "$1" = "stat" ]; then
+	expected_string="middle                          1"
+elif [ "$1" = "supercover" ]; then
+	expected_string="cell \$cover \$auto\$supercover"
+fi
+
+if [ "$expected_string" != "" ]; then
+if grep "$expected_string" result.log; then
+	if [ $expected = "1" ]; then
+		cell_failed="0"
+	else
+		cell_failed="1"
+	fi
+else
+	if [ $expected = "1" ]; then
+		cell_failed="1"
+	else
+		cell_failed="0"
+	fi
+fi
+fi
+
 if grep 'Assert' result.log || grep 'failed in' result.log || grep 'ERROR' result.log; then
 	echo FAIL > ${1}_${2}.status
+elif [ $cell_failed = '1' ]; then
+	echo FAIL > ${1}_${2}.status
 else
 	echo PASS > ${1}_${2}.status
 fi

misc/scripts/add.ys

 read_verilog ../top.v
-tee -o result.log add -wire w 0
+add -wire w 0
+tee -o result.log dump

misc/scripts/add_global_input.ys

 read_verilog ../top.v
-tee -o result.log add -global_input gi 32000
+add -global_input gi 32000
+tee -o result.log dump

misc/scripts/add_inout.ys

 read_verilog ../top.v
-tee -o result.log add -inout \34 3
+ add -inout \34 3
+tee -o result.log dump

misc/scripts/add_input.ys

 read_verilog ../top.v
 add -input i 2
-tee -o result.log add -input i 2
+add -input i 2
+tee -o result.log dump

misc/scripts/add_output.ys

 read_verilog ../top.v
-tee -o result.log add -output o 3
+add -output o 3
+tee -o result.log dump

misc/scripts/add_wire.ys

 read_verilog ../top.v
-tee -o result.log add -wire w 1
+add -wire w 1
+tee -o result.log dump

misc/scripts/assertpmux.ys

 read_verilog ../top.v
 proc
-tee -o result.log assertpmux
+assertpmux
+tee -o result.log dump

misc/scripts/assertpmux_always.ys

 read_verilog ../top.v
 proc
-tee -o result.log assertpmux -always
+assertpmux -always
+tee -o result.log dump

misc/scripts/assertpmux_noinit.ys

 read_verilog ../top.v
 proc
-tee -o result.log assertpmux -noinit
+assertpmux -noinit
+tee -o result.log dump

misc/scripts/blackbox.ys

 read_verilog ../top.v
-tee -o result.log blackbox bb
+blackbox bb
+tee -o result.log dump

misc/scripts/chformal.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -remove
+chformal -remove
+tee -o result.log dump

misc/scripts/chformal_assert.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -assert -remove
+chformal -assert -remove
+tee -o result.log dump

misc/scripts/chformal_assert2assume.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -assert2assume
+chformal -assert2assume
+tee -o result.log dump

misc/scripts/chformal_assume.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -assume -remove
+chformal -assume -remove
+tee -o result.log dump

misc/scripts/chformal_assume2assert.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -assume2assert
+chformal -assume2assert
+tee -o result.log dump

misc/scripts/chformal_fair.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -fair -remove
+tee -o res dump
+chformal -fair -remove
+tee -o result.log dump

misc/scripts/chformal_fair2live.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -fair2live
+chformal -fair2live
+tee -o result.log dump

misc/scripts/chformal_fair2live_assert2assume.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -fair2live -assert2assume
+chformal -fair2live -assert2assume
+tee -o result.log dump

misc/scripts/chformal_live.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -live -remove
+chformal -live -remove
+tee -o result.log dump

misc/scripts/chformal_live2fair.ys

 read_verilog -sv ../top.v
-tee -o result.log chformal -live2fair
+chformal -live2fair
+tee -o result.log dump

misc/scripts/chtype_set.ys

 read_verilog -sv ../top.v
 proc
+tee -o d.txt dump
 tee -o result.log chtype -set $adff $2
+tee -o d1.txt dump

misc/scripts/delete.ys

 read_verilog ../top.v
-tee -o result.log delete middle
+delete middle
+tee -o result.log dump

misc/scripts/delete_cell.ys

 read_verilog ../top.v
-tee -o result.log delete top/$1
+delete top/$2
+tee -o result.log dump

misc/scripts/delete_input.ys

 read_verilog ../top.v
-tee -o result.log delete -input middle/x
+tee -o res.log dump
+delete -input top/x
+tee -o result.log dump

misc/scripts/delete_mem.ys

 read_verilog ../top.v
-tee -o result.log delete top/$7
+delete top/$7
+tee -o result.log dump

misc/scripts/delete_output.ys

 read_verilog ../top.v
-tee -o result.log delete -output middle/o
+delete -output middle/o
+tee -o result.log dump

misc/scripts/delete_port.ys

 read_verilog ../top.v
-tee -o result.log delete -port top/A
+delete -port top/A
+tee -o result.log dump

misc/scripts/delete_proc.ys

 read_verilog ../top.v
-tee -o result.log delete top/$3
+tee -o resul.log dump
+delete top/$1
+tee -o result.log dump

misc/scripts/delete_wire.ys

 read_verilog ../top.v
-tee -o result.log delete top/o
+tee -o resul.log dump
+delete top/o
+tee -o result.log dump

misc/scripts/insbuf.ys

 read_verilog ../top.v
 synth
 insbuf
+tee -o result.log dump
 write_verilog synth.v

misc/scripts/insbuf_cell.ys

 read_verilog ../top.v
 synth
 insbuf -buf $_BUF_ A Y
+tee -o result.log dump
 write_verilog synth.v

misc/scripts/mutate_all.ys

 read_verilog ../top.v
 mutate -list 512 -o mutate.ys
 script mutate.ys
-
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
-#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
-#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
-#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -ctrlbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
-#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
-#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
-#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+tee -o result.log dump
 

misc/scripts/mutate_cnot0.ys

 read_verilog ../top.v
 tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+tee -o result.log dump
 
 
 

misc/scripts/mutate_cnot1.ys

 read_verilog ../top.v
 tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src top.v:12
+tee -o result.log dump
 
 
 

misc/scripts/mutate_const0.ys

 read_verilog ../top.v
 tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+tee -o result.log dump
 
 

misc/scripts/mutate_const1.ys

 read_verilog ../top.v
 tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+tee -o result.log dump
 
 
 

misc/scripts/mutate_inv.ys

 read_verilog ../top.v
 tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
 
+tee -o result.log dump
 

misc/scripts/pmuxtree.ys

 read_verilog ../top.v
 proc
-tee -o result.log pmuxtree
+pmuxtree
+tee -o result.log dump

misc/scripts/qwp.ys

 read_verilog ../top.v
 proc
-tee -o result.log qwp
+qwp
+tee -o result.log dump

misc/scripts/qwp_alpha.ys

 read_verilog ../top.v
 proc
-tee -o result.log qwp -alpha
+qwp -alpha
+tee -o result.log dump

misc/scripts/qwp_dump.ys

 read_verilog ../top.v
 proc
-tee -o result.log qwp -dump out.html
+qwp -dump out.html
+tee -o result.log dump

misc/scripts/qwp_grid.ys

 read_verilog ../top.v
 proc
-tee -o result.log qwp -grid 4
+qwp -grid 4
+tee -o result.log dump

misc/scripts/qwp_ltr.ys

 read_verilog ../top.v
 proc
-tee -o result.log qwp -ltr
+qwp -ltr
+tee -o result.log dump

misc/scripts/qwp_v.ys

 read_verilog ../top.v
 proc
-tee -o result.log qwp -v
+qwp -v
+tee -o result.log dump

misc/scripts/rename.ys

 read_verilog ../top.v
 proc
 tee -o result.log rename middle mid_module
+tee -o result.log dump

misc/scripts/rename_low.ys

 read_verilog ../top.v
 synth
 tee -o result.log rename low newlow
+tee -o result.log dump

misc/scripts/rename_top.ys

 read_verilog ../top.v
 synth -top top
 tee -o result.log rename -top new_top
+tee -o result.log dump

misc/scripts/rmports.ys

 read_verilog ../top.v
 proc
-tee -o result.log rmports
+rmports
+tee -o result.log dump

misc/scripts/scatter.ys

 read_verilog ../top.v
 proc
-tee -o result.log scatter
+scatter
+tee -o result.log dump

misc/scripts/setattr_mod.ys

 read_verilog ../top.v
 proc
 tee -o result.log setattr -mod -set u 1 top
+tee -o result.log dump

misc/scripts/setattr_set.ys

 read_verilog ../top.v
 proc
 tee -o result.log setattr -set u 1 top
+tee -o result.log dump

misc/scripts/setattr_set_proc.ys

 read_verilog ../top.v
 tee -o result.log setattr -set u 1 top
+tee -o result.log dump

misc/scripts/setattr_top.ys

 read_verilog ../top.v
 proc
 tee -o result.log setattr top
+tee -o result.log dump

misc/scripts/setattr_unset.ys

@@ -2,3 +2,4 @@ read_verilog ../top.v
 proc
 tee -o result.log setattr -set u 1 top
 tee -o result.log setattr -unset u top
+tee -o result.log dump

misc/scripts/splice.ys

 read_verilog ../top.v
-tee -o result.log splice
+splice
 proc
-tee -o result.log splice
+splice
 synth
-tee -o result.log splice
+splice
+tee -o result.log dump

misc/scripts/splice_no_outputs.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -no_outputs
+splice -no_outputs
+tee -o result.log dump

misc/scripts/splice_no_port.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -no_port q_b
+splice -no_port q_b
+tee -o result.log dump

misc/scripts/splice_port.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -port q_b
+splice -port data_a
+tee -o result.log dump

misc/scripts/splice_sel_any_bit.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -sel_any_bit
+splice -sel_any_bit
+tee -o result.log dump

misc/scripts/splice_sel_by_cell.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -sel_by_cell
+splice -sel_by_cell
+tee -o result.log dump

misc/scripts/splice_sel_by_wire.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -sel_by_wire
+splice -sel_by_wire
+tee -o result.log dump

misc/scripts/splice_wires.ys

 read_verilog ../top.v
 synth
-tee -o result.log splice -wires
+splice -wires
+tee -o result.log dump

misc/scripts/splitnets.ys

 read_verilog -sv ../top.v
-tee -o result.log splitnets
+splitnets
+tee -o result.log dump

misc/scripts/splitnets_dpf.ys

 read_verilog -sv ../top.v
-tee -o result.log splitnets -driver -ports -format www
+splitnets -driver -ports -format www
+tee -o result.log dump

misc/scripts/splitnets_driver.ys

 read_verilog -sv ../top.v
-tee -o result.log splitnets -driver
+splitnets -driver
+tee -o result.log dump

misc/scripts/splitnets_format.ys

 read_verilog -sv ../top.v
-tee -o result.log splitnets -format ()
+splitnets -format ()
+tee -o result.log dump

misc/scripts/splitnets_ports.ys

 read_verilog -sv ../top.v
-tee -o result.log splitnets -ports
+splitnets -ports
+tee -o result.log dump

misc/scripts/supercover.ys

 read_verilog ../top.v
 proc
+tee -o res.log dump
 tee -o result.log supercover
+tee -o result.log dump