Merge pull request #18 from YosysHQ/pr_00896

Add regression test for Yosys PR 896

regression/Makefile

@@ -339,6 +339,7 @@ $(eval $(call template,issue_00862,issue_00862))
 #issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
 $(eval $(call template,issue_00865,issue_00865))
 
+$(eval $(call template,pr_00896,pr_00896))
 
 
 .PHONY: all clean

regression/pr_00896/outreg.v

+module dut(
+	input fast_clk, slow_clk,
+	input [3:0] waddr, raddr,
+	input [3:0] wdata,
+	input wen,
+	output [3:0] rdata
+);
+
+	reg [3:0] mem[0:15];
+	reg [3:0] raddr_reg;
+
+	always @(posedge fast_clk) begin
+		if (wen)
+			mem[waddr] <= wdata;
+	end
+
+	always @(posedge slow_clk)
+		raddr_reg <= raddr;
+
+	assign rdata = mem[raddr_reg];
+endmodule

regression/pr_00896/testbench.v

+`include "../outreg.v"
+
+module tb;
+	reg fast_clk, slow_clk;
+
+	initial begin
+		$dumpfile("testbench.vcd");
+		$dumpvars(0, tb);
+		repeat (80) @(posedge slow_clk);
+		$display("OKAY");
+		$finish;
+	end
+
+	always #4 fast_clk = (fast_clk === 1'b0);
+	always #12 slow_clk = (slow_clk === 1'b0);
+
+	reg [7:0] wdata = 1;
+	always @(posedge fast_clk) wdata <= {wdata[6:0], wdata[7] ^ wdata[2]};
+
+	reg [3:0] waddr = 0;
+	always @(posedge fast_clk) waddr <= waddr + 1'b1;
+
+	reg [3:0] raddr = 0;
+	always @(posedge slow_clk) raddr <= raddr + 1'b1;
+
+
+	wire [3:0] rdata, rdata_postsyn;
+
+	dut dut_i(
+		.fast_clk(fast_clk), .slow_clk(slow_clk),
+		.raddr(raddr), .waddr(waddr), .wen(1'b1),
+		.wdata(wdata[3:0]), .rdata(rdata)
+	);
+
+	dut_syn dut_syn_i(
+		.fast_clk(fast_clk), .slow_clk(slow_clk),
+		.raddr(raddr), .waddr(waddr), .wen(1'b1),
+		.wdata(wdata[3:0]), .rdata(rdata_postsyn)
+	);
+	always @(posedge fast_clk)
+		if (rdata_postsyn != rdata) begin
+			$display("ERROR");
+			$finish;
+		end
+endmodule

regression/run.sh

@@ -150,6 +150,8 @@ else
 		 [ "$1" = "issue_00589" ] ||\
 		 [ "$1" = "issue_00628" ]; then
 		iverilog_adds="../../../../../techlibs/ice40/cells_sim.v"
+	elif [ "$1" = "pr_00896" ]; then
+		iverilog_adds="../../../../../techlibs/ecp5/cells_sim.v"
 	fi
 
 	yosys -ql yosys.log ../../scripts/$2.ys

regression/scripts/pr_00896.ys

+read_verilog ../outreg.v
+synth_ecp5
+rename dut dut_syn
+write_verilog -norename synth.v