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lvzhengyang
yosys-tests
Commits
8cb52aaf
Unverified
Commit
8cb52aaf
authored
Apr 27, 2019
by
Miodrag Milanović
Committed by
GitHub
Apr 27, 2019
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Merge pull request #25 from SergeyDegtyar/master
Test architecture/synth_gowin_mem fixed.
parents
3c248654
d7fb4009
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architecture/synth_gowin_mem/testbench.v
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architecture/synth_gowin_mem/testbench.v
View file @
8cb52aaf
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@@ -22,30 +22,11 @@ module testbench;
reg
mem_init
=
0
;
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;
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