Merge remote-tracking branch 'origin/master' into more_bigsim

architecture/Makefile

@@ -71,6 +71,7 @@ $(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_b
 $(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
+$(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
 endif
 
 #greenpak4

architecture/run.sh

@@ -2,7 +2,6 @@
 
 set -x
 test -d $1
-test -f scripts/$2.ys
 
 rm -rf $1/work_$2
 mkdir $1/work_$2
@@ -25,7 +24,6 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: Invalid Xilinx -family setting: "
 	fi
 
-
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
 		echo FAIL > ${1}_${2}.status
 	else
@@ -39,9 +37,15 @@ else
 
 	if [ -f ../run-test.sh ]; then
 		../run-test.sh
+		if [ $? != 0 ] ; then
+			echo FAIL > ${1}_${2}.status
+		else
+			echo PASS > ${1}_${2}.status
+		fi
 		touch .stamp
-		exit 0
+		exit
 	else
+		test -f scripts/$2.ys
 		yosys -ql yosys.log ../../scripts/$2.ys
 		if [ $? != 0 ] ; then
 			echo FAIL > ${1}_${2}.status

architecture/synth_xilinx_mux/assert_area.py

+#!/usr/bin/python3
+
+import glob
+import re
+import os
+
+re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
+
+area = {}
+#             1  2  3  4  5  6 F7 F8
+area[2]   = [ 0, 0, 1, 0, 0, 0, 0, 0 ]
+area[3]   = [ 0, 0, 0, 0, 1, 0, 0, 0 ]
+area[4]   = [ 0, 0, 0, 0, 0, 0, 2, 1 ]
+area[5]   = [ 0, 0, 1, 0, 0, 0, 2, 1 ]
+area[7]   = [ 0, 0, 3, 0, 0, 0, 2, 1 ]
+area[8]   = [ 0, 0, 4, 0, 0, 0, 2, 1 ]
+area[9]   = [ 0, 0, 3, 0, 1, 0, 2, 1 ]
+area[15]  = [ 0, 0, 0, 0, 1, 3, 2, 1 ]
+area[16]  = [ 0, 0, 0, 0, 0, 4, 2, 1 ]
+area[17]  = [ 0, 0, 1, 0, 0, 4, 2, 1 ]
+area[31]  = [ 0, 0, 1, 0, 1, 7, 4, 2 ]
+area[32]  = [ 0, 0, 1, 0, 0, 8, 4, 2 ]
+area[33]  = [ 0, 0, 0, 0, 1, 8, 4, 2 ]
+area[63]  = [ 0, 0, 0, 0, 1,15,10, 5 ]
+area[64]  = [ 0, 0, 0, 0, 0,16,10, 5 ]
+area[65]  = [ 0, 0, 1, 0, 0,16,10, 5 ]
+area[127] = [ 0, 0, 4, 0, 1,31,18, 9 ]
+area[128] = [ 0, 0, 4, 0, 0,32,18, 9 ]
+area[129] = [ 0, 0, 3, 0, 1,32,18, 9 ]
+area[255] = [ 0, 0, 0, 0, 1,67,34,17 ]
+area[256] = [ 0, 0, 0, 0, 0,68,34,17 ]
+area[257] = [ 0, 0, 1, 0, 0,68,34,17 ]
+
+for fn in glob.glob('*.v'):
+    m = re_mux.match(fn)
+    if not m: continue
+
+    N,W = map(int, m.group(2,3))
+    assert N in area
+
+    bn,_ = os.path.splitext(fn)
+
+    with open(fn, 'a') as f:
+        assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
+        print('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd; %s";
+endmodule
+`endif
+''' % '; '.join(assert_area), file=f)

architecture/synth_xilinx_mux/run-test.sh

+#!/bin/bash
+set -e
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/generate.py -O generate_small.py -o /dev/null
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/common.py -O common.py -o /dev/null
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
+python3 generate_small.py
+python3 generate_large.py
+python3 ../assert_area.py
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
+    -p 'design -copy-to __test __test; \
+        synth_xilinx -abc9 -widemux 4; \
+        design -copy-from __test *; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/xilinx/cells_sim.v"
+
+# Spot tests for -widemux thresholds
+set +e
+../../../../../yosys -qp "synth_xilinx -widemux 1" 2> /dev/null
+if [ $? -eq 0 ]; then
+    echo "Expected error"
+    exit 1
+fi
+set -e
+
+../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 1 t:MUXF7" mux_if_bal_2_1.v
+
+../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-count 6 t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 6 t:MUXF*" mux_case_3_3.v
+
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 9; select -assert-none t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 8; select -assert-none t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 7; select -assert-count 15 t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 6; select -assert-count 15 t:MUXF*" mux_index_7_5.v
+
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 18; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 17; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 16; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 15; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v

architecture/synth_xilinx_srl/generate.py

 #!/usr/bin/python3
+import re, glob
 
 N = 131
 
+def assert_static_area(fp, i, name):
+    if i < 3:
+        srl32,srl16,fd = (0,0,i)
+    else:
+        srl32 = i // 32
+        if (i % 32) == 0:
+            srl16 = 0
+            fd = 0
+        elif (i % 32) == 1:
+            srl16 = 0
+            fd = 1
+        elif (i % 32) <= 17:
+            srl16 = 1
+            fd = (i % 32) - 16
+        else:
+            srl32 += 1
+            srl16 = 0
+            fd = 0
+    fp.write('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; cd {3}_{4}; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none";
+endmodule
+`endif
+'''.format(fd, srl16, srl32, name, i))
+
+def assert_dynamic_area(fp, i, name):
+    if i < 3:
+        srl32,srl16,fd = (0,0,i)
+        lut3 = 1 if i > 1 else 0
+        lut5 = 0
+    else:
+        srl32 = i // 32
+        if (i % 128) == 0 or (i % 32) == 0:
+            srl16 = 0
+            fd = 0
+        elif (i % 128) == 1:
+            srl16 = 0
+            fd = 1
+        elif (i % 32) <= 16:
+            srl16 = 1
+            fd = 0
+        else:
+            srl32 += 1
+            srl16 = 0
+            fd = 0
+        lut3 = 1 if i > 128 and i < 257 else 0
+        lut5 = 1 if i > 256 else 0
+    muxf8 = (srl32+srl16) // 4
+    if ((srl32 + srl16) % 4) == 0:
+        muxf7 = muxf8 * 2
+    elif ((srl32 + srl16) % 4) == 3:
+        muxf8 += 1
+        muxf7 = muxf8 * 2
+    else:
+        muxf7 = (srl32+srl16) // 2
+    fp.write('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; select t:MUXF7 -assert-count {3}; select t:MUXF8 -assert-count {4}; select t:LUT3 -assert-count {5}; select t:LUT5 -assert-count {6}; cd {7}_{8}; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT3 t:LUT5 %% %n t:* %i -assert-none";
+endmodule
+`endif
+'''.format(fd, srl16, srl32, muxf7, muxf8, lut3, lut5, name, i))
+
+
 # Test 1: pos_clk_no_enable_no_init_not_inferred
 for i in range(1,N+1):
     with open('test1_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test1_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -20,11 +87,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test1')
 
 # Test 2: pos_clk_with_enable_no_init_not_inferred
 for i in range(1,N+1):
     with open('test2_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test2_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -39,11 +108,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test2')
 
 # Test 3: pos_clk_with_enable_with_init_inferred
 for i in range(1,N+1):
     with open('test3_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test3_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -65,11 +136,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test3')
 
 # Test 4: neg_clk_no_enable_no_init_not_inferred
 for i in range(1,N+1):
     with open('test4_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test4_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -84,11 +157,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test4')
 
 # Test 5: neg_clk_no_enable_no_init_inferred
 for i in range(1,N+1):
     with open('test5_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test5_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -107,11 +182,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test5')
 
 # Test 6: neg_clk_with_enable_with_init_inferred
 for i in range(1,N+1):
     with open('test6_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test6_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -133,11 +210,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test6')
 
 # Test 10: pos_clk_no_enable_no_init_not_inferred_var_len
 for i in range(1,N+1):
     with open('test10_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test10_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input [31:0] l, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -154,11 +233,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_dynamic_area(fp, i, 'test10')
 
 # Test 11: neg_clk_with_enable_with_init_inferred_var_len
 for i in range(1,N+1):
     with open('test11_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test11_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -180,11 +261,30 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_dynamic_area(fp, i, 'test11')
+
+import lfsr_area
+re_lfsr = re.compile(r'lfsr_(\d+)\.v')
+for fn in glob.glob('lfsr_*.v'):
+    m = re_lfsr.match(fn)
+    if not m: continue
+
+    W = int(m.group(1))
+
+    with open(fn, 'a') as f:
+        print('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "%s";
+endmodule
+`endif
+''' % lfsr_area.area[W], file=f)
 
 # Test 15: pos_clk_no_enable_no_init_not_inferred
 for i in range(128+1,128+N+1):
     with open('test15_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test15_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -199,11 +299,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_static_area(fp, i, 'test15')
 
 # Test 16: neg_clk_with_enable_with_init_inferred_var_len
 for i in range(128+1,128+N+1):
     with open('test16_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test16_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -225,11 +327,13 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+        assert_dynamic_area(fp, i, 'test16')
 
 # Test 18: neg_clk_with_enable_with_init_inferred2
 for i in range(1,N+1):
     with open('test18_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test18_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
 generate 
     reg [width-1:0] int [depth-1:0];
@@ -237,7 +341,7 @@ generate
     genvar w, d;
     for (d = 0; d < depth; d=d+1) begin
         for (w = 0; w < width; w=w+1) begin
-            initial int[d][w] <= ~((d+w) % 2);
+            //initial int[d][w] <= ~((d+w) % 2);
 
             if (d == 0) begin
                 always @(negedge clk) if (e) int[d][w] <= i[w];
@@ -250,11 +354,13 @@ generate
     assign q = int[depth-1];
 endgenerate
 endmodule'''.format(i))
+        assert_static_area(fp, i, 'test18')
 
 # Test 19: pos_clk_with_enable_no_init_inferred2_var_len
 for i in range(1,N+1):
     with open('test19_%d.v' % i, 'w') as fp:
         fp.write('''
+(* top *)
 module test19_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
 generate 
     reg [width-1:0] int [depth-1:0];
@@ -275,3 +381,4 @@ generate
     assign q = int[l];
 endgenerate
 endmodule'''.format(i))
+        assert_dynamic_area(fp, i, 'test19')

architecture/synth_xilinx_srl/run-test.sh

 #!/bin/bash
+set -e
 shopt -s extglob
 
 OPTIND=1
@@ -22,10 +23,19 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
 python3 generate_lfsr.py
 python3 ../generate.py
 cp ../*.v .
-${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../../techlibs/xilinx/cells_sim.v"
-${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../../techlibs/xilinx/cells_sim.v"
-
-cp ../*.ys .
-for ys in *.ys; do
-    yosys -q $ys
-done
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
+    -f 'verilog -noblackbox -icells' \
+    -p 'design -copy-to __test __test; \
+        synth_xilinx; \
+        design -copy-from __test __test; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/xilinx/cells_sim.v"
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="\
+    -f 'verilog -noblackbox -icells' \
+    -p 'design -copy-to __test __test; \
+        synth_xilinx -retime; \
+        design -copy-from __test __test; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/xilinx/cells_sim.v"

architecture/synth_xilinx_srl/test13.ys

-# Check that non chain users block SRLs
-design -reset; read_verilog test13a.out/test13a_syn0.v; select t:SRL* -assert-count 0
-design -reset; read_verilog test13b.out/test13b_syn0.v; select t:SRL* -assert-count 0
-design -reset; read_verilog test13c.out/test13c_syn0.v; select t:SRL* -assert-count 0
-design -reset; read_verilog test13d.out/test13d_syn0.v; select t:SRL* -assert-count 0

architecture/synth_xilinx_srl/test13a.v

 // Check that non chain users block SRLs
 // (i.e. output port, in non flattened case)
 // sr_fixed_length_other_users_port
+(* top *)
 module test13a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
 generate 
     wire [depth:0] int [width-1:0];
@@ -15,3 +16,9 @@ generate
     assign state = int[0][depth:1];
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test13a; select t:SRL* -assert-count 0";
+endmodule
+`endif

architecture/synth_xilinx_srl/test13b.v

 // Check that non chain users block SRLs
 // (i.e. output port, in non flattened case)
 // sr_var_length_other_users_port
+(* top *)
 module test13b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -22,3 +23,9 @@ generate
     assign state = int[0];
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test13b; select t:SRL* -assert-count 0";
+endmodule
+`endif

architecture/synth_xilinx_srl/test13c.v

 // Check that non chain users block SRLs
 // (i.e. output port, in non flattened case)
 // sr_fixed_length_other_users_xor
+(* top *)
 module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
 generate 
     wire [depth:0] int [width-1:0];
@@ -15,3 +16,9 @@ generate
     assign state = int[0][depth:1];
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test13c; select t:SRL* -assert-count 0";
+endmodule
+`endif

architecture/synth_xilinx_srl/test13d.v

 // Check that non chain users block SRLs
 // (i.e. output port, in non flattened case)
 // sr_var_length_other_users_xor
-module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
+(* top *)
+module test13d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
 generate 
     reg [depth-1:0] int [width-1:0];
 
@@ -22,3 +23,9 @@ generate
     assign state = {depth{^int[0]}};
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test13d; select t:SRL* -assert-count 0";
+endmodule
+`endif

architecture/synth_xilinx_srl/test17.ys

-design -reset; read_verilog test17a.out/test17a_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
-design -reset; read_verilog test17b.out/test17b_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
-design -reset; read_verilog test17c.out/test17c_syn0.v; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;
-design -reset; read_verilog test17d.out/test17d_syn0.v; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;
-design -reset; read_verilog test17e.out/test17e_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;

architecture/synth_xilinx_srl/test17a.v

 // Check inference even when not in vector
+(* top *)
 module test17a (input clk, input i, output q);
 generate 
     reg a1, a2, a3, a4, a5, a6, a7, a8;
@@ -13,3 +14,9 @@ generate
     assign q = a8;
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
+endmodule
+`endif

architecture/synth_xilinx_srl/test17b.v

 // Check inference even when not in vector
-module test17a (input clk, input i, input e, output q);
+(* top *)
+module test17b (input clk, input i, input e, output q);
 generate 
    reg a1, a2, a3, a4, a5, a6, a7, a8;
    always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
    assign q = a8;
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
+endmodule
+`endif

architecture/synth_xilinx_srl/test17c.v

 // Check inference even when keep attribute specified
+(* top *)
 module test17c (input clk, input i, input e, output q);
 generate 
     reg a1, a2, a3;
@@ -8,3 +9,9 @@ generate
     assign q = a8;
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;";
+endmodule
+`endif

architecture/synth_xilinx_srl/test17d.v

 // Check inference even when keep attribute specified
+(* top *)
 module test17d (input clk, input i, input e, output q);
 generate 
     reg a1, a2;
@@ -9,3 +10,9 @@ generate
     assign q = a8;
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;";
+endmodule
+`endif

architecture/synth_xilinx_srl/test17e.v

 // Check inference even when keep attribute specified
-module test17d (input clk, input i, input e, output q);
+(* top *)
+module test17e (input clk, input i, input e, output q);
 generate 
     reg a1, a2;
     (* blah *) reg a3;
@@ -11,3 +12,9 @@ generate
 endgenerate
 endmodule
 
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
+endmodule
+`endif

architecture/synth_xilinx_srl/test20.v

+(* top *)
 module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
 generate 
     reg [width-1:0] int [depth-1:0];
@@ -18,3 +19,9 @@ generate
     assign z = int[depth-1];
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test20; select t:FD* -assert-count 0";
+endmodule
+`endif

architecture/synth_xilinx_srl/test20.ys

-design -reset; read_verilog test20.out/test20_syn0.v; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/test21.ys

-# Check that retiming does not infer shift registers
-design -reset; read_verilog test21a.out/test21a_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
-design -reset; read_verilog test21b.out/test21b_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20

architecture/synth_xilinx_srl/test21a.v

+(* top *)
 module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
     genvar d;
     wire [depth:0] int;
@@ -9,3 +10,9 @@ module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i,
     endgenerate 
     assign q = int[depth];
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test21a; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
+endmodule
+`endif

architecture/synth_xilinx_srl/test21b.v

+(* top *)
 module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
     reg [depth-1:0] int;
 
@@ -14,3 +15,9 @@ module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i,
         assign q = int[depth-1];
     end
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test21b; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
+endmodule
+`endif

architecture/synth_xilinx_srl/test7.ys

-# Check that shift registers with resets are not inferred into SRLs
-design -reset; read_verilog test7a.out/test7a_syn0.v; select t:SRL* -assert-count 0
-design -reset; read_verilog test7b.out/test7b_syn0.v; select t:SRL* -assert-count 0
-design -reset; read_verilog test7c.out/test7c_syn0.v; select t:SRL* -assert-count 0
-design -reset; read_verilog test7d.out/test7d_syn0.v; select t:SRL* -assert-count 0

architecture/synth_xilinx_srl/test7a.v

 // Check that use of resets block shreg
 // pos_clk_no_enable_no_init_not_inferred_with_reset
+(* top *)
 module test7a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -13,3 +14,9 @@ generate
     end
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test7a; select t:SRL* -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/test7b.v

 // Check that use of resets block shreg
 // neg_clk_no_enable_with_init_with_inferred_with_reset
+(* top *)
 module test7b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -20,3 +21,9 @@ generate
     end
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test7b; select t:SRL* -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/test7c.v

 // Check that use of resets block shreg
 // pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
+(* top *)
 module test7c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -15,3 +16,9 @@ generate
     end
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test7c; select t:SRL* -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/test7d.v

 // Check that use of resets block shreg
 // neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
+(* top *)
 module test7d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -20,3 +21,9 @@ generate
     end
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test7d; select t:SRL* -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/test8.v

 // Check multi-bit works
 // pos_clk_no_enable_no_init_not_inferred_N_width
+(* top *)
 module test8 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
@@ -13,3 +14,9 @@ generate
     end
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test8; select t:FD* -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/test8.ys

-# Check that wide shift registers are not a problem
-read_verilog test8.out/test8_syn0.v; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/test9.v

 // Check multi-bit works
 // neg_clk_no_enable_with_init_with_inferred_N_width
+(* top *)
 module test9 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
@@ -20,3 +21,9 @@ generate
     end
 endgenerate
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd test9; select t:FD* -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/test9.ys

-read_verilog test9.out/test9_syn0.v; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/ug901.ys

-design -reset; read_verilog ug901a.out/ug901a_syn0.v; select t:SRLC32E -assert-count 1
-design -reset; read_verilog ug901b.out/ug901b_syn0.v; select t:SRLC32E -assert-count 1
-design -reset; read_verilog ug901c.out/ug901c_syn0.v; select t:SRLC32E -assert-count 1

architecture/synth_xilinx_srl/ug901a.v

@@ -5,6 +5,7 @@
 // Active high clock enable
 // Concatenation-based template
 // File: shift_registers_0.v
+(* top *)
 module shift_registers_0 (clk, clken, SI, SO);
 parameter WIDTH = 32;
 input clk, clken, SI;
@@ -17,3 +18,9 @@ begin
 end
 assign SO = shreg[WIDTH-1];
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/ug901b.v

@@ -5,6 +5,7 @@
 // Active high clock enable
 // For-loop based template
 // File: shift_registers_1.v
+(* top *)
 module shift_registers_1 (clk, clken, SI, SO);
 parameter WIDTH = 32;
 input clk, clken, SI;
@@ -23,3 +24,8 @@ end
 assign SO = shreg[WIDTH-1];
 endmodule
 
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
+endmodule
+`endif

architecture/synth_xilinx_srl/ug901c.v

@@ -3,6 +3,7 @@
 // 32-bit dynamic shift register.
 // Download:
 // File: dynamic_shift_registers_1.v
+(* top *)
 module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
 parameter SELWIDTH = 5;
 input CLK, CE, SI;
@@ -17,3 +18,9 @@ always @(posedge CLK)
  data <= {data[DATAWIDTH-2:0], SI};
  end
 endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
+endmodule
+`endif

backends/Makefile

@@ -35,7 +35,7 @@ $(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor
 $(eval $(call template,write_btor_pmux,write_btor_pmux))
 $(eval $(call template,write_btor_and_or,write_btor_and_or))
 $(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
-$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type write_btor_no_driver))
+$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type))
 
 #write_edif
 $(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
@@ -76,7 +76,7 @@ $(eval $(call template,write_simplec_error,write_simplec_no_c_model write_simple
 #write_smt2
 $(eval $(call template,write_smt2,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 $(eval $(call template,write_smt2_logic,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
-$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
+$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
 $(eval $(call template,write_smt2_fsm,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 $(eval $(call template,write_smt2_init_assert,write_smt2_init_assert))
 $(eval $(call template,write_smt2_reduce,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))

backends/run.sh

@@ -33,8 +33,6 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: No top module found."
 	elif [ "$2" = "write_btor_unsupported_cell_type" ]; then
 		expected_string="ERROR: Unsupported cell type: "
-	elif [ "$2" = "write_btor_no_driver" ]; then
-		expected_string="ERROR: No driver for signal bit "
 	elif [ "$2" = "write_edif_cyclic_dependency" ]; then
 		expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
 	elif [ "$2" = "write_edif_constant_nodes" ]; then

backends/scripts/write_btor.ys

@@ -8,6 +8,7 @@ synth -top top
 write_btor btor1.btor
 design -reset
 read_verilog -sv ../top.v
+proc_prune
 proc_init
 proc_mux
 proc_dff

backends/scripts/write_btor_no_driver.ys

-read_verilog ../top.v
-memory
-write_btor btor.btor

backends/scripts/write_btor_s.ys

@@ -7,6 +7,7 @@ synth -top top
 write_btor -s btor1.btor
 design -reset
 read_verilog -sv ../top.v
+proc_prune
 proc_init
 proc_mux
 proc_dff

backends/scripts/write_btor_v.ys

@@ -7,6 +7,7 @@ synth -top top
 write_btor -v btor1.btor
 design -reset
 read_verilog -sv ../top.v
+proc_prune
 proc_init
 proc_mux
 proc_dff
@@ -51,4 +52,4 @@ write_btor -v btor10.btor
 design -reset
 read_verilog  -sv ../top_clean.v
 synth -top top
-write_verilog synth.v 
+write_verilog synth.v

frontends/Makefile

@@ -27,6 +27,7 @@ $(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read
 $(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
 $(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
 $(eval $(call template,read_blif_eblif,read_blif_eblif))
+$(eval $(call template,read_blif_error, read_blif_syntax_error read_blif_duplicate_defenition ))
 
 #read_ilang
 $(eval $(call template,read_ilang,read_ilang read_ilang_selected))
@@ -34,6 +35,7 @@ $(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected))
 $(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected))
 $(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected))
 $(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
+$(eval $(call template,read_ilang_error,read_ilang_parse_error))
 
 #read_json
 $(eval $(call template,read_json,read_json))
@@ -42,6 +44,7 @@ $(eval $(call template,read_json_logic,read_json))
 $(eval $(call template,read_json_mem,read_json_mem))
 $(eval $(call template,read_json_mux,read_json))
 $(eval $(call template,read_json_tri,read_json))
+$(eval $(call template,read_json_error, read_json_nonstring_key read_json_nonarray_bits_attr read_json_unexpected_eof read_json_invalid_direction read_json_no_bits read_json_no_direction read_json_unexpected_char ))
 
 #read_liberty  read_liberty_lib
 $(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
@@ -55,6 +58,7 @@ $(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite
 $(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
 $(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
 $(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_error, read_liberty_invalid_bus_type read_liberty_unsupp_type_for_bus read_liberty_bus_interface_only_in_lib_mode read_liberty_latch_has_no_data_in read_liberty_miss_func_on_output read_liberty_ff_has_no_next_stage_attr read_liberty_parse_error_in_function read_liberty_cant_resolve_wire_name read_liberty_missing_direction read_liberty_cant_open_input_file read_liberty_redefenition_of_module ))
 
 #read_aiger
 $(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_clk read_aiger_clk_module ))
@@ -62,6 +66,7 @@ $(eval $(call template,read_aiger_latch,read_aiger_aig))
 $(eval $(call template,read_aiger_logic,read_aiger_aig))
 $(eval $(call template,read_aiger_ff,read_aiger_aig))
 $(eval $(call template,read_aiger_mult,read_aiger_aig))
+$(eval $(call template,read_aiger_error, read_aiger_cant_interpret_first_char read_aiger_unsup_aiger_file read_aiger_invalid_aiger_header read_aiger_cant_interpret_as_input read_aiger_cant_interpret_as_and read_aiger_bad_state_property read_aiger_invalid_reset_literal read_aiger_duplicate_definition ))
 
 #read
 # read_vhdl87 read_vhdl93 read_vhdl2k read_vhdl2008 read_vhdl - ERROR: This version of Yosys is built without Verific support.
@@ -72,9 +77,11 @@ $(eval $(call template,read_verilog,read_verilog read_verilog_assert_assumes rea
 
 #verilog_defaults
 $(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push verilog_defaults_pop verilog_defaults_clear))
+$(eval $(call template,verilog_defaults_error,verilog_defaults_missing_arg verilog_defaults_extra_arg))
 
 #verilog_defines
 $(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
+$(eval $(call template,verilog_defines_error,verilog_defines_extra_arg))
 
 #verilog_lexer
 $(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))

frontends/read_aiger_error/aiger_ff1.aiger

+aaga 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_ff2.aiger

+aag 7 2 1 2 4 a
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_ff3.aiger

+aag 7 2 1 2 4
+2 s
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_ff4.aiger

+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7f
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_latch1.aiger

+aag 1 0 1 2 0 2
+2 3
+2
+3

frontends/read_aiger_error/aiger_latch2.aiger

+aag 1 0 1 2 0
+2 3 3
+2
+3

frontends/read_aiger_error/aiger_latch3.aiger

+aag 1 0 1 2 0
+2 3
+21
+3

frontends/read_blif_error/blif_e1.blif

+# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+
+.modell top
+.inputs C S[0] S[1]
+.outputs Y[0] Y[1] Y[2] Y[3]
+.names $false
+.names $true
+1
+.names $undef
+.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
+.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
+.names $false $1\Y[3:0][0]
+1 1
+.names $false $1\Y[3:0][1]
+1 1
+.names $false $1\Y[3:0][2]
+1 1
+.names $false $1\Y[3:0][3]
+1 1
+.names $procmux$3_Y[0] $0\Y[3:0][0]
+1 1
+.names $procmux$3_Y[1] $0\Y[3:0][1]
+1 1
+.names $procmux$3_Y[2] $0\Y[3:0][2]
+1 1
+.names $procmux$3_Y[3] $0\Y[3:0][3]
+1 1
+.end

frontends/read_blif_error/blif_seg_fault.blif

+# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+
+.model top
+.inputs C S[0] S[1]
+.outputs Y[0] Y[1] Y[2] Y[3]
+.names $false
+.names $true
+1
+.names $undef
+.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
+.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
+.names $false $1\Y[3:0][0]
+1 1
+.names
+1 1
+.names $false $1\Y[3:0][2]
+1 1
+.names $false $1\Y[3:0][3]
+1 1
+.names $procmux$3_Y[0] $0\Y[3:0][0]
+1 1
+.names $procmux$3_Y[1] $0\Y[3:0][1]
+1 1
+.names $procmux$3_Y[2] $0\Y[3:0][2]
+1 1
+.names $procmux$3_Y[3] $0\Y[3:0][3]
+1 1
+.end

frontends/read_blif_error/eblif_seg_fault.eblif

+
+.model top
+.names a b
+.inputs a
+.outputs b
+.conn a b
+.names a b c
+11 1
+.cname $my_and_gate
+.latch a_and_b dff_q re clk 0
+.attr my_design.v:42
+.end

frontends/read_blif_error/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

frontends/read_ilang_error/file.il

+
+autoidx 15
+
+attribute \cells_not_processed 1
+attribute \src "top.v:1"
+module \top
+
+  attribute \src "top.v:17"
+  wire $0\B[0:0]
+
+  attribute \src "top.v:19"
+  attribute \unused_bits "1"
+  wire width 2 $and$top.v:19$4_Y
+
+  attribute \src "top.v:18"
+  wire $logic_and$top.v:18$2_Y
+
+  attribute \src "top.v:20"
+  wire $logic_and$top.v:20$6_Y
+
+  attribute \src "top.v:20"
+  wire $logic_not$top.v:20$5_Y
+
+  attribute \src "top.v:18"
+  wire $logic_or$top.v:18$3_Y
+
+  attribute \src "top.v:20"
+  wire $logic_or$top.v:20$7_Y
+
+  attribute \src "top.v:21"
+  attribute \unused_bits "1"
+  wire width 2 $or$top.v:21$8_Y
+
+  wire $procmux$10_Y
+
+  attribute \src "top.v:8"
+  wire input 5 \A
+
+  attribute \init 1'0
+  attribute \src "top.v:9"
+  wire output 6 \B
+
+  attribute \src "top.v:6"
+  wire input 4 \clk
+
+  attribute \src "top.v:3"
+  wire width 2 input 1 \x
+
+  attribute \src "top.v:4"
+  wire width 2 input 2 \y
+
+  attribute \src "top.v:5"
+  wire width 2 input 3 \z
+
+  attribute \src "top.v:19"
+  cell $and $and$top.v:19$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \z
+    connect \Y $and$top.v:19$4_Y
+  end
+
+  attribute \src "top.v:18"
+  cell $logic_and $logic_and$top.v:18$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B \z
+    connect \Y $logic_and$top.v:18$2_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_and $logic_and$top.v:20$6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B $logic_not$top.v:20$5_Y
+    connect \Y $logic_and$top.v:20$6_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_not $logic_not$top.v:20$5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \z
+    connect \Y $logic_not$top.v:20$5_Y
+  end
+
+  attribute \src "top.v:18"
+  cell $logic_or $logic_or$top.v:18$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:18$2_Y
+    connect \Y $logic_or$top.v:18$3_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_or $logic_or$top.v:20$7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:20$6_Y
+    connect \Y $logic_or$top.v:20$7_Y
+  end
+
+  attribute \src "top.v:21"
+  cell $or $or$top.v:21$8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \x
+    connect \Y $or$top.v:21$8_Y
+  end
+
+  attribute \src "top.v:17"
+  cell $dff $procdff$14
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D $0\B[0:0]
+    connect \Q \B
+  end
+
+  attribute \src "top.v:18"
+  cell $mux $procmux$10
+    parameter \WIDTH 1
+    connect \A \B
+    connect \B $and$top.v:19$4_Y [0]
+    connect \S $logic_or$top.v:18$3_Y
+    connect \Y $procmux$10_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $mux $procmux$12
+    parameter \WIDTH 1
+    connect \A $procmux$10_Y
+    connect \B $or$top.v:21$8_Y [0]
+    connect \S $logic_or$top.v:20$7_Y
+    connect \Y $0\B[0:0]
+  end
+end

frontends/read_ilang_error/ilang.ilang

+# Generated by Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+autoidx 15
+attribute \cells_not_processed 1
+attribute \src "top.v:1"
+module \top
+  attribute \src "top.v:17"
+  wire $0\B[0:0]
+  attribute \src "top.v:19"
+  attribute \unused_bits "1"
+  wire width 2 $and$top.v:19$4_Y
+  attribute \src "top.v:18"
+  wire $logic_and$top.v:18$2_Y
+  attribute \src "top.v:20"
+  wire $logic_and$top.v:20$6_Y
+  attribute \src "top.v:20"
+  wire $logic_not$top.v:20$5_Y
+  attribute \src "top.v:18"
+  wire $logic_or$top.v:18$3_Y
+  attribute \src "top.v:20"
+  wire $logic_or$top.v:20$7_Y
+  attribute \src "top.v:21"
+  attribute \unused_bits "1"
+  wire width 2 $asdfasdfasfor$top.v:21$8_Y
+  wire $procmux$10_Y
+  attribute \src "top.v:8"
+  wire input 5 \A
+  attribute \init 1'0
+  attribute \src "top.v:9"
+  wire output 6 \B
+  attribute \src "top.v:6"
+  wire input 4 \clk
+  attribute \src "top.v:3"
+  wire width 2 input 1 \x
+  attribute \src "top.v:4"
+  wire width 2 input 2 \y
+  attribute \src "top.v:5"
+  wire width 2 input 3 \z
+  attribute \src "top.v:19"
+  cell $and $and$top.v:19$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \z
+    connect \Y $and$top.v:19$4_Y
+  end
+  attribute \src "top.v:18"
+  cell $logic_and $logic_and$top.v:18$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B \z
+    connect \Y $logic_and$top.v:18$2_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_and $logic_and$top.v:20$6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B $logic_not$top.v:20$5_Y
+    connect \Y $logic_and$top.v:20$6_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_not $logic_not$top.v:20$5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \z
+    connect \Y $logic_not$top.v:20$5_Y
+  end
+  attribute \src "top.v:18"
+  cell $logic_or $logic_or$top.v:18$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:18$2_Y
+    connect \Y $logic_or$top.v:18$3_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_or $logic_or$top.v:20$7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:20$6_Y
+    connect \Y $logic_or$top.v:20$7_Y
+  end
+  attribute \src "top.v:21"
+  cell $or $or$top.v:21$8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \x
+    connect \Y $or$top.v:21$8_Y
+  end
+  attribute \src "top.v:17"
+  cell $dff $procdff$14
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D $0\B[0:0]
+    connect \Q \B
+  end
+  attribute \src "top.v:18"
+  cell $mux $procmux$10
+    parameter \WIDTH 1
+    connect \A \B
+    connect \B $and$top.v:19$4_Y [0]
+    connect \S $logic_or$top.v:18$3_Y
+    connect \Y $procmux$10_Y
+  end
+  attribute \src "top.v:20"
+  cell $mux $procmux$12
+    parameter \WIDTH 1
+    connect \A $procmux$10_Y
+    connect \B $or$top.v:21$8_Y [0]
+    connect \S $logic_or$top.v:20$7_Y
+    connect \Y $0\B[0:0]
+  end
+end

frontends/read_ilang_error/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

frontends/read_ilang_error/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

frontends/read_json_error/json1.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "directisson": "inpusdfsdft",
+          "bitsss": [ a ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
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frontends/read_json_error/json2.json

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frontends/read_json_error/json3.json

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frontends/read_json_error/json4.json

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frontends/read_json_error/json5.json

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frontends/read_json_error/json6.json

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+}

frontends/read_json_error/json7.json

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frontends/read_json_error/json8.json

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+}

frontends/read_liberty_error/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib1.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : 2 ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib2.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!s)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib3.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A*)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib4.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/libff.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+clocked_on : " CLK ";
+clear : " CLR ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_error/liblat.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "latch";
+latch(IQ, IQN) {
+enable : "CLK" ;
+clear : "CLR" ;}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_error/liblat1.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "latch";
+latch(IQ, IQN) {
+enable : "CLK" ;
+data_in : "D" ;
+clear : "CLR" ;}
+type ( BUS4 ) {
+ base_type : arraysss ;
+ data_type : bit ;
+ bit_width : 4 ;
+ bit_from : 0 ;
+ bit_to : 3 ;
+ downto :false ;
+}
+bus(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_error/liblat2.lib

+library (ExamBus) {
+date : "May 14, 2002";
+ revision : 2002.05;
+ bus_naming_style :"%s[%d]";/* Optional; this is the
+ default */
+type (bus4) {
+base_type : array;/* Required */
+data_type : bit;/* Required if base_type is array */
+bit_width : 4;/* Optional; default is 1 */
+bit_from : 0;/* Optional MSB; defaults to 0 */
+bit_to : 3;/* Optional LSB; defaults to 0 */
+downto : false;/* Optional; defaults to false */
+}
+cell (bused_cell) {
+area : 10;
+bus (A) {
+bus_type : bus4;
+direction : input;
+capacitance : 3;
+pin (A[0:2]) {
+capacitance : 2;
+}
+pin (A[3]) {
+ capacitance : 2.5;
+}
+}
+bus (B) {
+bus_type : bus4;
+capacitance : 2;
+}
+pin (E) {
+direction : input ;
+capacitance : 2 ;
+}
+bus(X) {
+bus_type : bus4;
+direction : output;
+capacitance : 1;
+pin (X[0:3]) {
+function : "A & B’";
+timing() {
+related_pin : "A B";
+/* A[0] and B[0] are related to X[0],
+A[1] and B[1] are related to X[1], etc. */
+}
+}
+}
+bus (Y) {
+bus_type : bus4;
+direction : output;
+capacitance : 1;
+pin (Y[0:3]) {
+function : "B";
+three_state : "!E";
+timing () {
+related_pin : "A[0:3] B E";
+}
+internal_power() {
+when: "E" ;
+related_pin : B ;
+power() {
+}
+}
+internal_power() {
+related_pin : B ;
+power() {
+}
+}
+}
+}
+bus (Z) {
+bus_type : bus4;
+direction : output;
+pin (Z[0:1]) {
+function : "!A[0:1]";
+timing () {
+related_pin : "A[0:1]";
+}
+internal_power() {
+related_pin  : "A[0:1]";
+power() {
+}
+}
+}
+pin (Z[2]) {
+function : "A[2]";
+timing () {
+related_pin : "A[2]";
+}
+internal_power() {
+related_pin : "A[0:1]";
+power() {
+}
+}
+}
+pin (Z[3]) {
+function : "!A[3]";
+timing () {
+related_pin : "A[3]";
+}
+internal_power() {
+related_pin : "A[0:1]";
+power() {
+}
+}
+}
+}
+pin_opposite("Y[0:1]","Z[0:1]");
+/* Y[0] is opposite to Z[0], etc. */
+pin_equal("Y[2:3] Z[2:3]");
+ /* Y[2], Y[3], Z[2], and Z[3] are equal */
+cell (bused_cell2) {
+area : 20;
+bus (A) {
+bus_type : bus41;
+direction : input;
+capacitance : 1;
+pin (A[0:3]) {
+capacitance : 2;
+}
+pin (A[3]) {
+capacitance : 2.5;
+}
+}
+bus (B) {
+bus_type : bus4;
+direction : input;
+capacitance : 2;
+}
+pin (E) {
+direction : input ;
+capacitance : 2 ;
+bus(X) {
+bus_type : bus4;
+direction : output;
+capacitance : 1;
+pin (X[0:3]) {
+function : "A & B’";
+timing() {
+related_pin : "A B";
+/* A[0] and B[0] are related to X[0],
+A[1] and B[1] are related to X[1], etc. */
+}
+}
+}
+}

regression/issue_00449/testbench.v → frontends/read_liberty_error/testbench.v

 module testbench;
-    reg clk;
+    reg a;
+
+	wire b;
 
     initial begin
-       // $dumpfile("testbench.vcd");
-       // $dumpvars(0, testbench);
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
 
-        #0 clk = 0;
+        #5 a = 0;
         repeat (10000) begin
-            #5 clk = 1;
-            #5 clk = 0;
+            #5 a = ~a;
         end
 
         $display("OKAY");
     end
 
-	wire b;
-
-	top uut (clk,b);
+    top uut (
+	.A(a),
+	.Y(b)
+	);
 
-	assert_X b_test(.clk(clk), .A(b));
+	assert_comb b_test(.A(~a),.B(b));
 
 endmodule

frontends/run.sh

@@ -10,34 +10,120 @@ cd $1/work_$2
 
 touch .start
 
-yosys -ql yosys.log ../../scripts/$2.ys
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
-sed -i 's/reg =/dummy =/' ./synth.v
+# cases where 'syntax error' or other errors are expected
+if echo "$1" | grep ".*_error"; then
 
-if [ -f "../../../../../techlibs/common/simcells.v" ]; then
-    COMMON_PREFIX=../../../../../techlibs/common
-else
-    COMMON_PREFIX=/usr/local/share/yosys
-fi
+	expected_string=""
+    #Change checked string for check other errors
+	if [ "$2" = "read_aiger_cant_interpret_first_char" ]; then
+		expected_string="ERROR: Line 80: cannot interpret first character"
+	elif [ "$2" = "read_aiger_unsup_aiger_file" ]; then
+		expected_string="ERROR: Unsupported AIGER file!"
+	elif [ "$2" = "read_aiger_invalid_aiger_header" ]; then
+		expected_string="ERROR: Invalid AIGER header"
+	elif [ "$2" = "read_aiger_cant_interpret_as_input" ]; then
+		expected_string="ERROR: Line 2 cannot be interpreted as an input!"
+	elif [ "$2" = "read_aiger_cant_interpret_as_and" ]; then
+		expected_string="ERROR: Line 6 cannot be interpreted as an AND!"
+	elif [ "$2" = "read_aiger_bad_state_property" ]; then
+		expected_string="ERROR: Line 4 cannot be interpreted as a bad state property!"
+	elif [ "$2" = "read_aiger_invalid_reset_literal" ]; then
+		expected_string="ERROR: Line 1 has invalid reset literal for latch!"
+	elif [ "$2" = "read_aiger_duplicate_definition" ]; then
+		expected_string="ERROR: Duplicate definition of module top!"
+	elif [ "$2" = "read_blif_syntax_error" ]; then
+		expected_string="ERROR: Syntax error in line"
+	elif [ "$2" = "read_blif_duplicate_defenition" ]; then
+		expected_string="ERROR: Duplicate definition of module "
+	elif [ "$2" = "read_ilang_parse_error" ]; then
+		expected_string="ERROR: Parser error in line "
+	elif [ "$2" = "read_json_nonstring_key" ]; then
+		expected_string="ERROR: Unexpected non-string key in JSON dict."
+	elif [ "$2" = "read_json_nonarray_bits_attr" ]; then
+		expected_string=" has non-array bits attribute."
+	elif [ "$2" = "read_json_unexpected_eof" ]; then
+		expected_string="ERROR: Unexpected EOF in JSON file."
+	elif [ "$2" = "read_json_invalid_direction" ]; then
+		expected_string="ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute."
+	elif [ "$2" = "read_json_no_bits" ]; then
+		expected_string=" has no bits attribute."
+	elif [ "$2" = "read_json_no_direction" ]; then
+		expected_string=" has no direction attribute."
+	elif [ "$2" = "read_json_unexpected_char" ]; then
+		expected_string="ERROR: Unexpected character in JSON file: "
+	elif [ "$2" = "verilog_defaults_missing_arg" ]; then
+		expected_string="ERROR: Command syntax error: Missing argument."
+	elif [ "$2" = "verilog_defaults_extra_arg" ]; then
+		expected_string="ERROR: Command syntax error: Extra argument."
+	elif [ "$2" = "verilog_defines_extra_arg" ]; then
+		expected_string="ERROR: Command syntax error: Extra argument."
+	elif [ "$2" = "read_liberty_invalid_bus_type" ]; then
+		expected_string="ERROR: Missing or invalid direction for bus B on cell bused_cell."
+	elif [ "$2" = "read_liberty_unsupp_type_for_bus" ]; then
+		expected_string="ERROR: Unknown or unsupported type for bus interface D on cell top."
+	elif [ "$2" = "read_liberty_bus_interface_only_in_lib_mode" ]; then
+		expected_string="ERROR: Error in cell top: bus interfaces are only supported in -lib mode."
+	elif [ "$2" = "read_liberty_latch_has_no_data_in" ]; then
+		expected_string="ERROR: Latch cell top has no data_in and/or enable attribute."
+	elif [ "$2" = "read_liberty_miss_func_on_output" ]; then
+		expected_string="ERROR: Missing function on output Y of cell top."
+	elif [ "$2" = "read_liberty_ff_has_no_next_stage_attr" ]; then
+		expected_string="ERROR: FF cell top has no next_state and/or clocked_on attribute."
+	elif [ "$2" = "read_liberty_parse_error_in_function" ]; then
+		expected_string="ERROR: Parser error in function expr "
+	elif [ "$2" = "read_liberty_cant_resolve_wire_name" ]; then
+		expected_string="ERROR: Can't resolve wire name s."
+	elif [ "$2" = "read_liberty_missing_direction" ]; then
+		expected_string="ERROR: Missing or invalid direction for pin A on cell top."
+	elif [ "$2" = "read_liberty_cant_open_input_file" ]; then
+		expected_string="ERROR: Can't open input file \`../libbbb.lib' for reading: No such file or directory"
+	elif [ "$2" = "read_liberty_redefenition_of_module" ]; then
+		expected_string="ERROR: Re-definition of cell/module top!"
+	fi
 
-iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
 
-if ! vvp -N testbench > testbench.log 2>&1; then
-	grep 'ERROR' testbench.log
-	echo FAIL > ${1}_${2}.status
-elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo FAIL > ${1}_${2}.status
+	if yosys -ql yosys.log ../../scripts/$2.ys; then
+		echo FAIL > ${1}_${2}.status
+	else
+		if  grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
+			echo PASS > ${1}_${2}.status
+		else
+			echo FAIL > ${1}_${2}.status
+		fi
+	fi
 else
-	echo PASS > ${1}_${2}.status
+
+
+	yosys -ql yosys.log ../../scripts/$2.ys
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+	sed -i 's/reg =/dummy =/' ./synth.v
+
+	if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+		COMMON_PREFIX=../../../../../techlibs/common
+	else
+		COMMON_PREFIX=/usr/local/share/yosys
+	fi
+
+	iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+
+	if ! vvp -N testbench > testbench.log 2>&1; then
+		grep 'ERROR' testbench.log
+		echo FAIL > ${1}_${2}.status
+	elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo PASS > ${1}_${2}.status
+	fi
+
 fi
 
 touch .stamp

frontends/scripts/read_aiger_bad_state_property.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch1.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_cant_interpret_as_and.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff4.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_cant_interpret_as_input.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff3.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_cant_interpret_first_char.ys

+read_aiger -clk_name clk -module_name top ../aiger1.aiger
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_duplicate_definition.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
+read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_invalid_aiger_header.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff2.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_invalid_reset_literal.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch2.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_unsup_aiger_file.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff1.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_blif_duplicate_defenition.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_syntax_error.ys

+read_blif ../blif_e1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_ilang_parse_error.ys

+read_ilang ../ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v

frontends/scripts/read_json_invalid_direction.ys

+read_json ../json4.json
+write_verilog synth.v

frontends/scripts/read_json_no_bits.ys

+read_json ../json3.json
+write_verilog synth.v