bigsim: enable -retime and -dff options too

bigsim/Makefile

@@ -21,11 +21,11 @@ $(1)/.stamp_%: $(1)/.stamp_sim
 
 clean::
 	rm -rf $(1)/.stamp_* $(1)/work_*
-	rm -f $(1)_{cmos,ice40,falsify,ecp5,xilinx}{,_abc9}.status
+	rm -f $(1)_{cmos,ice40,falsify,ecp5,xilinx}{,_retime,_abc9,_abc9_dff}.status
 endef
 
-$(eval $(call template,navre,cmos ice40 ice40_abc9 ecp5 ecp5_abc9 xilinx xilinx_abc9))
+$(eval $(call template,navre,cmos ice40 ice40_retime ice40_abc9 ecp5 ecp5_retime ecp5_abc9 xilinx xilinx_retime xilinx_abc9 xilinx_abc9_dff))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
-$(eval $(call template,picorv32,cmos ice40 ice40_abc9 ecp5 ecp5_abc9 xilinx xilinx_abc9))
+$(eval $(call template,picorv32,cmos ice40 ice40_retime ice40_abc9 ecp5 ecp5_retime ecp5_abc9 xilinx xilinx_retime xilinx_abc9 xilinx_abc9_dff))
 endif
 .PHONY: all clean

bigsim/run.sh

@@ -36,6 +36,10 @@ case "$2" in
 		yosys -ql synthlog.txt -p "$PRESYN; synth_ice40 -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ice40/cells_sim.v"
 		;;
+	ice40_retime)
+		yosys -ql synthlog.txt -p "$PRESYN; synth_ice40 -retime -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ice40/cells_sim.v"
+		;;
 	ice40_abc9)
 		yosys -ql synthlog.txt -p "$PRESYN; synth_ice40 -abc9 -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ice40/cells_sim.v"
@@ -44,6 +48,10 @@ case "$2" in
 		yosys -ql synthlog.txt -p "$PRESYN; synth_ecp5 -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v -I$TECHLIBS_PREFIX/ecp5"
 		;;
+	ecp5_retime)
+		yosys -ql synthlog.txt -p "$PRESYN; synth_ecp5 -retime -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v -I$TECHLIBS_PREFIX/ecp5"
+		;;
 	ecp5_abc9)
 		yosys -ql synthlog.txt -p "$PRESYN; synth_ecp5 -abc9 -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v -I$TECHLIBS_PREFIX/ecp5"
@@ -52,10 +60,18 @@ case "$2" in
 		yosys -ql synthlog.txt -p "$PRESYN; synth_xilinx -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
 		;;
+	xilinx_retime)
+		yosys -ql synthlog.txt -p "$PRESYN; synth_xilinx -retime -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
+		;;
 	xilinx_abc9)
 		yosys -ql synthlog.txt -p "$PRESYN; synth_xilinx -abc9 -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
 		;;
+	xilinx_abc9_dff)
+		yosys -ql synthlog.txt -p "$PRESYN; synth_xilinx -abc9 -dff -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
+		;;
 	*)
 		exit 1
 		;;