fix

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys

@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 
 design -load postopt
 cd cmult
+stat
 #Vivado synthesizes 3 DSP48E1, 68 FDRE.
 select -assert-count 1 t:BUFG
 select -assert-count 86 t:FDRE
 select -assert-count 3 t:DSP48E1
 select -assert-count 34 t:LUT2
-select -assert-count 17 t:MUXCY
-select -assert-count 19 t:XORCY
+select -assert-count 6 t:CARRY4
 
-select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:CARRY4 %% t:* %D