Skip to content

Y
yosys-tests
Commit 842b5751 by Miodrag Milanovic
Options

fix

parent e0ace89f
Showing with 3 additions and 3 deletions
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
...@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter ...@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
design -load postopt design -load postopt
cd cmult cd cmult
stat
#Vivado synthesizes 3 DSP48E1, 68 FDRE. #Vivado synthesizes 3 DSP48E1, 68 FDRE.
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 86 t:FDRE select -assert-count 86 t:FDRE
select -assert-count 3 t:DSP48E1 select -assert-count 3 t:DSP48E1
select -assert-count 34 t:LUT2 select -assert-count 34 t:LUT2
select -assert-count 17 t:MUXCY select -assert-count 6 t:CARRY4
select -assert-count 19 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:CARRY4 %% t:* %D
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment