Fix test cases

backends/write_intersynth/write_intersynth__memory.pat

-node ram $mem RD_EN CONST_1_0x0 RD_DATA $memrd$\\ram$../../common/memory.v:19$6_DATA RD_ADDR addr_a RD_CLK CONST_1_0x0 WR_EN $memwr$\\ram$../../common/memory.v:16$1_EN WR_DATA $memwr$\\ram$../../common/memory.v:16$1_DATA WR_ADDR $memwr$\\ram$../../common/memory.v:16$1_ADDR WR_CLK CONST_1_0x0 RD_TRANSPARENT '0 RD_CLK_POLARITY '0 RD_CLK_ENABLE '0 RD_PORTS 0x1 WR_CLK_POLARITY '0 WR_CLK_ENABLE '0 WR_PORTS 0x1 INIT '00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ABITS 0x6 SIZE 0x40 OFFSET 0x0 WIDTH 0x8 MEMID 0x5c72616d
+node ram $mem WR_DATA $memwr$\\ram$../../common/memory.v:16$1_DATA WR_ADDR
\ No newline at end of file

backends/write_smv/write_smv__memory.ys

 read_verilog ../../common/memory.v
 proc
 memory
+dffunmap
 write_smv result.out

backends/write_spice/write_spice__memory.pat

-X1186 1189.0 1189.1 1189.2 1189.3 1189.4 1189.5 1189.6 1189.7 q_a.0 q_a.1 q_a.2 q_a.3 q_a.4 q_a.5 q_a.6 q_a.7 clk _dff
+X1187 ram_63_.0 ram_63_.1 ram_63_.2 ram_63_.3 ram_63_.4 ram_63_.5 ram_63_.6 ram_63_.7 17 15 13 11 9 7 4 1189 clk _dff