Merge pull request #34 from SergeyDegtyar/master

Add tests for commits: Add "wreduce -keepdc"; Add "fmcombine -initeq …

architecture/Makefile

@@ -58,7 +58,7 @@ $(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
 $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime synth_sf2_vlog synth_sf2_noiobs synth_sf2_clkbuf ))
 
 #xilinx
-$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr))
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl))
 
 #greenpak4
 $(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))

architecture/scripts/synth_xilinx_arch_xc6s.ys

+read_verilog ../top.v
+synth_xilinx -arch xc6s
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xc7.ys

+read_verilog ../top.v
+synth_xilinx -arch xc7
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xcu.ys

+read_verilog ../top.v
+synth_xilinx -arch xcu
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xcup.ys

+read_verilog ../top.v
+synth_xilinx -arch xcup
+write_verilog synth.v

architecture/scripts/synth_xilinx_nobram.ys

+read_verilog ../top.v
+synth_xilinx -nobram
+write_verilog synth.v

architecture/scripts/synth_xilinx_nodram.ys

+read_verilog ../top.v
+synth_xilinx -nodram
+write_verilog synth.v

architecture/scripts/synth_xilinx_nosrl.ys

+read_verilog ../top.v
+synth_xilinx -nosrl
+write_verilog synth.v

misc/Makefile

@@ -36,7 +36,7 @@ $(eval $(call template,trace_mem,trace_mem ))
 $(eval $(call template,write_file,write_file write_file_a ))
 
 #stat
-$(eval $(call template,stat, stat stat_top stat_width stat_liberty ))
+$(eval $(call template,stat, stat stat_top stat_width stat_liberty stat_tech_xilinx))
 
 #show
 # show_pause - skipped
@@ -190,7 +190,7 @@ $(eval $(call template,mutate, mutate_list mutate_cnot1 mutate_cnot0 mutate_cons
 $(eval $(call template,mutate_mem, mutate_list mutate_all))
 
 #fmconbine
-$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd))
+$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd fmcombine_anyeq fmcombine_initeq))
 
 #pmuxtree
 $(eval $(call template,pmuxtree, pmuxtree))

misc/scripts/fmcombine.ys

 read_verilog ../top.v
+proc
 tee -o result.log fmcombine top u_mid1 u_mid3
 tee -o result.log fmcombine top u_mid2 u_mid4
 tee -o result.log fmcombine top u_mid1_u_mid3 u_mid2_u_mid4

misc/scripts/fmcombine_anyeq.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -anyeq top u_mid1 u_mid2
+

misc/scripts/fmcombine_initeq.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -initeq top u_mid1 u_mid2
+

simple/Makefile

@@ -172,7 +172,11 @@ $(eval $(call template,opt_lut, opt_lut opt_lut_limit opt_lut_dlogic opt_lut_lim
 $(eval $(call template,opt_lut_ice40, opt_lut opt_lut_limit opt_lut_dlogic opt_lut_limit_0))
 
 #wreduce -memx
-$(eval $(call template,wreduce_memx, wreduce_memx))
+$(eval $(call template,wreduce_memx, wreduce wreduce_memx wreduce_keepdc wreduce_memx_keepdc))
+$(eval $(call template,wreduce_reduce, wreduce wreduce_memx wreduce_keepdc wreduce_memx_keepdc))
+$(eval $(call template,wreduce_adder, wreduce wreduce_memx wreduce_keepdc wreduce_memx_keepdc))
+$(eval $(call template,wreduce_mul, wreduce wreduce_memx wreduce_keepdc wreduce_memx_keepdc))
+$(eval $(call template,wreduce_div, wreduce wreduce_memx wreduce_keepdc wreduce_memx_keepdc))
 
 #opt_merge -share_all
 $(eval $(call template,opt_merge_share_all, opt_merge_share_all))

simple/scripts/wreduce.ys

+read_verilog ../top.v
+hierarchy -top top
+proc; opt; memory; dff2dffe; wreduce; clean; opt
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog -noexpr -norename synth.v

simple/scripts/wreduce_keepdc.ys

+read_verilog ../top.v
+hierarchy -top top
+proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog -noexpr -norename synth.v

simple/scripts/wreduce_memx_keepdc.ys

+read_verilog ../top.v
+hierarchy -top top
+proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog -noexpr -norename synth.v

simple/wreduce_adder/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

simple/wreduce_adder/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

simple/wreduce_div/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+         $dumpfile("testbench.vcd");
+         $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+	assert_X out_test(.clk(in[0]), .A(out));
+	assert_X carry_test(.clk(in[0]), .A(carryout));
+
+endmodule
+

simple/wreduce_div/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin % y / x;
+`else
+assign {cout,A} =  2'bXX;
+`endif
+
+endmodule

simple/wreduce_mul/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+	assign {patt_carry_out,patt_out} =  in[2] * in[1] * in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

simple/wreduce_mul/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin * y * x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

simple/wreduce_reduce/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+       // $dumpfile("testbench.vcd");
+       // $dumpvars(0, testbench);
+
+        #0 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+    reg [1:0] a = 0;
+    reg rst = 0;
+
+
+    top uut (
+		.x(x),
+		.clk(clk),
+		.rst(rst),
+		.a(a)
+    );
+
+
+    always @(posedge clk) begin
+
+    a <= a + 1;
+    end
+
+	always @(posedge clk) begin
+    #2;
+	rst <= !rst;
+    end
+
+	uut_checker q_test(.clk(clk), .en(rst), .A(x));
+endmodule
+
+
+
+module uut_checker(input clk, input en, input A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & A === 1'bz)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/wreduce_reduce/top.v

+// File: design.v
+// Generated by MyHDL 0.8
+// Date: Tue Dec  3 04:33:14 2013
+
+
+`timescale 1ns/10ps
+
+module top (
+    x,clk,rst,a
+);
+
+output x;
+reg x;
+input clk;
+input [2:0] rst;
+input [1:0] a;
+
+wire rst_or;
+
+assign rst_or = |rst;
+`ifndef BUG
+always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
+    reg i;
+    if (!rst_or) begin
+        i = 0;
+        x = 0;
+    end
+    else begin
+        case (a)
+            2'b00: begin
+				x = 0;
+                i = 0;
+            end
+            2'b01: begin
+                x = i;
+            end
+            2'b10: begin
+                i = 1;
+            end
+            2'b11: begin
+                i = 0;
+            end
+            default: begin
+                x = 0;
+                i = 0;
+            end
+        endcase
+    end
+end
+
+    `else
+always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
+    reg i;
+    if (!rst_or) begin
+        i = 0;
+        x = 0;
+    end
+    else begin
+        case (a)
+            2'b00: begin
+				x = 1'bZ;
+                i = 0;
+            end
+            2'b01: begin
+                x = 1'bZ;
+            end
+            2'b10: begin
+                i = 1;
+            end
+            2'b11: begin
+                i = 0;
+            end
+            default: begin
+                x = 1'bZ;
+                i = 0;
+            end
+        endcase
+    end
+end
+`endif
+endmodule