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yosys-tests
Commit 7b99379c by Eddie Hung
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Remove -norename

parent 0fcb2414
Showing with 1 additions and 1 deletions
architecture/synth_xilinx_srl/test10.ys
......@@ -2,7 +2,7 @@ read_verilog -icells -DTEST10 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog -norename synth10.v
write_verilog synth10.v
#cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[0].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[1].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
......
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