Skip to content

Y
yosys-tests
Commit 79c0b9ff by Miodrag Milanovic
Options

removed vpr param check

parent ec58e672
Showing with 0 additions and 28 deletions
architecture/synth_xilinx/synth_xilinx_vpr.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment