Add test22 to check SRLs can still get inferred for -retime too

architecture/synth_xilinx_srl/test22.ys

+read_verilog -icells -DTEST22 ../top.v
+synth_xilinx -retime -flatten
+rename -top synth
+clean -purge
+write_verilog synth22.v
+
+# Check that retiming can still infer shift registers
+select t:SRL* -assert-min 1
+select t:FD* -assert-min 16

architecture/synth_xilinx_srl/top.v

@@ -138,6 +138,11 @@ generate
     assign w2 = ~^a[`N-1:`N/2];
     shift_reg #(.depth(8), .neg_clk(1), .inferred(1), .init(1)) sr1 (clk, w2, r, /*l*/, z[1], /* state */);
     assign z[`N-1:2] = 'b0; // Suppress no driver warning
+`elsif TEST22
+    wire w;
+    assign w = ^a[`N-1:0];
+    shift_reg #(.depth(16), .inferred(1)) sr1 (clk, w, r, /*l*/, z[0], /* state */);
+    assign z[`N-1:1] = 'b0; // Suppress no driver warning
 `endif
 endgenerate
 endmodule