Add new tests to 'simple' test group

regression/scripts/issue_00589.ys

@@ -8,7 +8,7 @@ opt_clean
 opt
 wreduce
 alumacc
-share
+share -aggressive -force
 opt
 fsm
 opt -fast

simple/Makefile

@@ -149,6 +149,8 @@ $(eval $(call template,fsm_command, fsm_command fsm_fm_set_fsm_file fsm_encfile
 
 #share
 $(eval $(call template,share, share share_force share_aggressive share_fast share_limit))
+$(eval $(call template,share_shr, share share_force share_aggressive share_fast share_limit))
+$(eval $(call template,share_macc, share_force_macc share_aggressive_macc share_fast_macc share_limit_macc share_macc))
 #+ yosys -ql yosys.log ../../scripts/share_force.ys
 #ERROR: Abort in passes/opt/share.cc:724.
 #make: *** [Makefile:152: share_fsm/work_share_force/.stamp] Error 1

simple/scripts/share_aggressive_macc.ys

+read_verilog ../top.v
+proc
+flatten
+alumacc
+share -aggressive
+synth -top top
+write_verilog synth.v

simple/scripts/share_fast_macc.ys

+read_verilog ../top.v
+proc
+flatten
+alumacc
+share -fast
+synth -top top
+write_verilog synth.v

simple/scripts/share_force_macc.ys

+read_verilog ../top.v
+proc
+#flatten
+alumacc
+share -force
+synth -top top
+write_verilog synth.v

simple/scripts/share_limit_macc.ys

+read_verilog ../top.v
+proc
+flatten
+alumacc
+share -limit 1
+synth -top top
+write_verilog synth.v

simple/scripts/share_macc.ys

+read_verilog ../top.v
+proc
+alumacc
+share
+synth -top top
+write_verilog synth.v

simple/share_macc/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [24:0] dinA;
+    reg [17:0] dinB;
+    reg carryin;
+    reg rst;
+	wire [47:0] p;
+
+    top uut_macc (
+        .p (p),
+        .a (dinA),
+        .b (dinB),
+        .carryin (carryin ),
+        .clk (clk),
+        .rst (rst)
+    );
+    
+    initial begin
+        rst <= 0;
+        #5
+        rst <= 1;
+        #5
+        
+        @(posedge clk);
+        
+        dinA <= 38;
+        dinB <= 22;
+        carryin <= 1;
+        
+        repeat (10) @(posedge clk);
+        
+        dinA <= 0;
+        dinB <= 0;
+        carryin <= 0;
+        
+        repeat (10) @(posedge clk);
+        
+        dinA <= 33;
+        dinB <= 12;
+        carryin <= 0;
+        
+        repeat (10) @(posedge clk);
+        
+        dinA <= 0;
+        dinB <= 0;
+        carryin <= 0;
+    end
+	
+	uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
+  
+endmodule
+
+
+module uut_macc_checker(input clk, input [24:0] A, input [17:0] B, input C, input [47:0] P);
+	reg [47:0] p;
+	always @(posedge clk)
+    begin
+		#20
+		p <= (A * B) + C; 
+        if (P != p)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
+            //$stop;
+        end
+    end
+endmodule

simple/share_macc/top.v

+module MACC (P, A, B, CARRYIN, CLK, RST);
+
+  output reg [47:0] P;
+  input [24:0] A;
+  input [17:0] B;
+  input CARRYIN;
+  input CLK;
+  input RST;
+
+  reg [47:0] mult_reg;
+
+  always @(posedge CLK)
+    begin
+    if(!RST)
+        mult_reg <= 'b0;
+    else
+        mult_reg <= A * B;
+    end
+
+    always@(posedge CLK)
+    begin
+    if(!RST)
+        P <= 'b0;
+    else
+`ifndef BUG
+        P <= mult_reg + CARRYIN;
+`else
+        P <= mult_reg - CARRYIN;
+`endif
+    end
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input [24:0] a,
+input [17:0] b,
+input carryin,
+output [47:0] p,
+output [47:0] pw
+);
+
+MACC u_MACC (
+        .P (p),
+        .A (a),
+        .B (b ),
+        .CARRYIN (carryin ),
+        .CLK (clk),
+        .RST (rst)
+    );
+
+MACC u_MACC_1 (
+        .P (pw),
+        .A (a),
+        .B (b ),
+        .CARRYIN (~carryin ),
+        .CLK (~clk),
+        .RST (~rst)
+    );
+
+endmodule
+

simple/share_shr/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg in;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .in(in),
+              .out(f));
+
+    always @(posedge clk) begin
+    #3
+    in <= ~in;
+    end
+
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/share_shr/top.v

+module top    (
+out,
+clk,
+in
+);
+    output [7:0] out;
+    input clk, in;
+    reg signed [7:0] out;
+
+    always @(posedge clk)
+	begin
+		out    <= out >> 1;
+		out[7] <= in;
+	end
+
+endmodule