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lvzhengyang
yosys-tests
Commits
7664abcf
Commit
7664abcf
authored
Aug 01, 2019
by
Eddie Hung
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architecture/synth_xilinx_dsp/assert_area.py
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architecture/synth_xilinx_dsp/assert_area.py
View file @
7664abcf
...
@@ -22,12 +22,14 @@ for fn in glob.glob('*.v'):
...
@@ -22,12 +22,14 @@ for fn in glob.glob('*.v'):
if
A
<
B
:
if
A
<
B
:
A
,
B
=
B
,
A
A
,
B
=
B
,
A
Asigned
,
Bsigned
=
Bsigned
,
Asigned
Asigned
,
Bsigned
=
Bsigned
,
Asigned
X
=
(
A
+
23
)
//
24
if
A
==
25
:
if
X
>
1
and
A
%
24
==
1
:
X
=
1
# No headroom needed on single multiplier
X
-=
1
# No headroom needed on last multiplier
else
:
Y
=
(
B
+
16
)
//
17
X
=
(
A
+
23
)
//
24
if
Y
>
1
and
B
%
17
==
1
:
if
B
==
18
:
Y
-=
1
# No headroom needed on last multiplier
Y
=
1
# No headroom needed on single multiplier
else
:
Y
=
(
B
+
16
)
//
17
count_MAC
=
X
*
Y
count_MAC
=
X
*
Y
count_DFF
=
0
count_DFF
=
0
if
Preg
:
if
Preg
:
...
...
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