Add macc tests

architecture/synth_xilinx_dsp/generate_macc.py

+#!/usr/bin/env python3
+
+from common_macc import gen_macc
+
+ARange = ['17','17s','18','18s','19','19s','24','24s']
+BRange = ['17','17s']
+
+if __name__ == "__main__":
+    gen_macc(ARange, BRange, reg="ABM")

architecture/synth_xilinx_dsp/run-test.sh

@@ -21,7 +21,10 @@ fi
 #wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/generate.py -O generate_mul.py -o /dev/null
 cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
 PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
+cp ~/yosys/yosys-bench/verilog/benchmarks_small/macc/common.py common_macc.py
+PYTHONPATH=".:$PYTHONPATH" python3 ../generate_macc.py
 python3 ../assert_area.py
+cp ../*.v .
 ${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
     -p 'design -copy-to __test __test; \
         synth_xilinx; \