Fix test

architecture/synth_xilinx/synth_xilinx_nowidelut.ys

@@ -23,10 +23,10 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -noio
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 11 t:LUT2
-select -assert-count 3 t:LUT3
-select -assert-count 7 t:LUT4
+select -assert-count 10 t:LUT2
+select -assert-count 6 t:LUT3
+select -assert-count 5 t:LUT4
 select -assert-count 2 t:LUT5
-select -assert-count 31 t:LUT6
+select -assert-count 32 t:LUT6
 select -assert-count 3 t:CARRY4
 select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:CARRY4 %% t:* %D