Fix tests

architecture/synth_xilinx_srl/test17a.v

 // Check inference even when not in vector
+(* top *)
 module test17a (input clk, input i, output q);
 generate 
     reg a1, a2, a3, a4, a5, a6, a7, a8;

architecture/synth_xilinx_srl/test17b.v

 // Check inference even when not in vector
-module test17a (input clk, input i, input e, output q);
+(* top *)
+module test17b (input clk, input i, input e, output q);
 generate 
    reg a1, a2, a3, a4, a5, a6, a7, a8;
    always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};

architecture/synth_xilinx_srl/test17c.v

 // Check inference even when keep attribute specified
+(* top *)
 module test17c (input clk, input i, input e, output q);
 generate 
     reg a1, a2, a3;

architecture/synth_xilinx_srl/test17d.v

 // Check inference even when keep attribute specified
+(* top *)
 module test17d (input clk, input i, input e, output q);
 generate 
     reg a1, a2;

architecture/synth_xilinx_srl/test17e.v

 // Check inference even when keep attribute specified
-module test17d (input clk, input i, input e, output q);
+(* top *)
+module test17e (input clk, input i, input e, output q);
 generate 
     reg a1, a2;
     (* blah *) reg a3;

architecture/synth_xilinx_srl/test20.v

@@ -24,4 +24,4 @@ endmodule
 module __test ;
     wire [4095:0] assert_area = "cd test20; select t:FD* -assert-count 0";
 endmodule
-`endi
+`endif