Fine tune test21

architecture/synth_xilinx_srl/test21.ys

 read_verilog -icells -DTEST21 ../top.v
 synth_xilinx -retime -flatten
-#synth_xilinx -nosrl
 rename -top synth
 clean -purge
 write_verilog synth21.v
 
 # Check that retiming does not infer shift registers
-#select t:SRL* -assert-count 0
+select t:SRL* -assert-count 0
+select t:FD* -assert-min 13

architecture/synth_xilinx_srl/top.v

@@ -132,10 +132,11 @@ generate
     (* keep *)
     shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred2_N_width(clk, a, r, /*l*/, z, /* state */);
 `elsif TEST21
-    wire w;
-    assign w = ^a[`N-1:0];
-    shift_reg #(.depth(4)) sr0 (clk, w, 1'b1, /*l*/, z[0], /* state */);
-    shift_reg #(.depth(8), .neg_clk(1), .inferred(1), .init(1)) sr1 (clk, ~w, r, /*l*/, z[1], /* state */);
+    wire w1, w2;
+    assign w1 = ^a[`N/2-1:0];
+    shift_reg #(.depth(4)) sr0 (clk, w1, 1'b1, /*l*/, z[0], /* state */);
+    assign w2 = ~^a[`N-1:`N/2];
+    shift_reg #(.depth(8), .neg_clk(1), .inferred(1), .init(1)) sr1 (clk, w2, r, /*l*/, z[1], /* state */);
     assign z[`N-1:2] = 'b0; // Suppress no driver warning
 `endif
 endgenerate