Unverified Commit 6a8cb072 by Eddie Hung Committed by GitHub

Merge pull request #14 from YosysHQ/verific_chparam

[tests] Add -chparam option to verific command
parents 472fed36 b81c0b34
all: test1.status test2.status test3.status test4.status test5.status
@grep -H . *.status | sed 's,.status:,\t,; s,PASS,pass,;' | expand -t20
@touch .stamp
test1.status: test1.out
@(grep -q -e "^Importing module top_veri_v2k(WIDTH=2).$$" $< && \
grep -q -e "^Importing module top_veri_95(WIDTH=2).$$" $< && \
grep -q -e "^Importing module top_vhdl(width=2).$$" $< && \
echo PASS > $@) || echo FAIL > $@
test2.status: test2.out
@(grep -q -e "^Importing module top_veri_v2k(greeting=\"hola hola\").$$" $< && \
grep -q -e "^Importing module top_veri_95(greeting=\"hola hola\").$$" $< && \
grep -q -e "^Importing module top_vhdl(greeting=\"hola hola\").$$" $< && \
echo PASS > $@) || echo FAIL > $@
test3.status: test3.out
@(grep -q -e "^Importing module top_veri_v2k.$$" $< && \
grep -q -e "^Importing module top_veri_95.$$" $< && \
grep -q -e "^Importing module top_vhdl.$$" $< && \
grep -q -e "^VERIFIC-WARNING \\[VHDL-1676\\] top.vhd:1: unit 'top_vhdl' does not have a generic named 'nonexistent' to override$$" $< && \
grep -q -e "^VERIFIC-WARNING \\[VERI-1928\\] top.v:1: module 'top_veri_v2k' does not have a parameter named 'nonexistent' to override$$" $< && \
grep -q -e "^VERIFIC-WARNING \\[VERI-1928\\] top.v:10: module 'top_veri_95' does not have a parameter named 'nonexistent' to override$$" $< && \
echo PASS > $@) || echo FAIL > $@
test4.status: test4.out
@(grep -q -e "^Importing module top_veri_v2k.$$" $< && \
grep -q -e "^Importing module top_veri_95.$$" $< && \
grep -q -e "^Importing module top_vhdl.$$" $< && \
grep -q -e "^-chparam WIDTH already specified: overwriting.$$" $< && \
echo PASS > $@) || echo FAIL > $@
test5.status: test5.out
@(grep -q -e "^Importing module top_veri_v2k(WIDTH=2,INIT=0,greeting=\"bonjour \").$$" $< && \
grep -q -e "^Importing module top_veri_95(WIDTH=2,INIT=0,greeting=\"bonjour \").$$" $< && \
grep -q -e "^Importing module top_vhdl(width=2,init='0',greeting=\"bonjour \").$$" $< && \
grep -q -e "^VERIFIC-WARNING \\[VHDL-1676\\] top.vhd:1: unit 'top_vhdl' does not have a generic named 'nonexistent' to override$$" $< && \
grep -q -e "^VERIFIC-WARNING \\[VERI-1928\\] top.v:1: module 'top_veri_v2k' does not have a parameter named 'nonexistent' to override$$" $< && \
grep -q -e "^VERIFIC-WARNING \\[VERI-1928\\] top.v:10: module 'top_veri_95' does not have a parameter named 'nonexistent' to override$$" $< && \
echo PASS > $@) || echo FAIL > $@
test1.out test2.out test3.out test4.out test5.out: test.ys top.v top.vhd
@yosys -q -q test.ys
clean:
rm -f *.status *.out .stamp
.PHONY: all clean
# Regular override integer
verific -sv top.v
verific -vhdl top.vhd
tee -o test1.out verific -import -chparam WIDTH 2 top_veri_v2k top_veri_95 top_vhdl
# Regular override string
design -reset
verific -sv top.v
verific -vhdl top.vhd
tee -o test2.out verific -import -chparam greeting "hola hola" top_veri_v2k top_veri_95 top_vhdl
# Non-existent overrides
design -reset
verific -sv top.v
verific -vhdl top.vhd
tee -o test3.out verific -import -chparam nonexistent 12345678 top_veri_v2k top_veri_95 top_vhdl
# Duplicate overrides
design -reset
verific -sv top.v
verific -vhdl top.vhd
tee -o test4.out verific -import -chparam WIDTH 3 -chparam WIDTH 1 top_veri_v2k top_veri_95 top_vhdl
# All of the above
design -reset
verific -sv top.v
verific -vhdl top.vhd
tee -o test5.out verific -import -chparam WIDTH 9999 -chparam WIDTH 2 -chparam INIT 0 -chparam greeting "bonjour " -chparam nonexistent 12345678 top_veri_v2k top_veri_95 top_vhdl
module top_veri_v2k #(parameter WIDTH=1, INIT=1, greeting="hello") (input clk, input [WIDTH-1:0] i, output reg o);
initial begin
o <= INIT;
$display("%s", greeting);
end
always @(posedge clk)
o <= ^i;
endmodule
module top_veri_95(clk, i, o);
parameter WIDTH=1;
parameter INIT=1;
parameter greeting="hello";
input clk;
input [WIDTH-1:0] i;
output o;
reg o;
initial begin
o <= INIT;
$display("%s", greeting);
end
always @(posedge clk)
o <= ^i;
endmodule
entity top_vhdl is
generic (WIDTH : integer := 1; INIT : bit := '1'; greeting : string(1 to 9) := "hello ");
port (clk : in bit; i : in bit_vector(WIDTH-1 downto 0); o : out bit := INIT);
end entity;
architecture rtl of top_vhdl is
begin
process
begin
report greeting;
--wait;
end process;
process (clk)
begin
if rising_edge(clk) then
o <= xor i;
end if;
end process;
end rtl;
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