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lvzhengyang
yosys-tests
Commits
69ee7e02
Commit
69ee7e02
authored
Aug 28, 2020
by
Miodrag Milanovic
Browse files
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Plain Diff
Rename ilang to rtlil
parent
627a3d12
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Showing
22 changed files
with
30 additions
and
30 deletions
+30
-30
frontends/read_rtlil/error.il
+0
-0
frontends/read_rtlil/file.il
+0
-0
frontends/read_rtlil/read_rtlil.ys
+2
-2
frontends/read_rtlil/read_rtlil_fsm.ys
+2
-2
frontends/read_rtlil/read_rtlil_lib.ys
+2
-2
frontends/read_rtlil/read_rtlil_lib_fsm.ys
+2
-2
frontends/read_rtlil/read_rtlil_lib_tri.ys
+3
-3
frontends/read_rtlil/read_rtlil_mem.ys
+2
-2
frontends/read_rtlil/read_rtlil_mux.ys
+2
-2
frontends/read_rtlil/read_rtlil_nooverwrite.ys
+2
-2
frontends/read_rtlil/read_rtlil_nooverwrite_fsm.ys
+2
-2
frontends/read_rtlil/read_rtlil_overwrite.ys
+2
-2
frontends/read_rtlil/read_rtlil_overwrite_fsm.ys
+2
-2
frontends/read_rtlil/read_rtlil_parse_error.ys
+1
-1
frontends/read_rtlil/read_rtlil_selected.ys
+2
-2
frontends/read_rtlil/read_rtlil_selected_fsm.ys
+2
-2
frontends/read_rtlil/read_rtlil_tri.ys
+2
-2
frontends/read_rtlil/top.v
+0
-0
frontends/read_rtlil/top_fsm.v
+0
-0
frontends/read_rtlil/top_mem.v
+0
-0
frontends/read_rtlil/top_mux.v
+0
-0
frontends/read_rtlil/top_tri.v
+0
-0
No files found.
frontends/read_
ilang/ilang.ilang
→
frontends/read_
rtlil/error.il
View file @
69ee7e02
File moved
frontends/read_
ilang
/file.il
→
frontends/read_
rtlil
/file.il
View file @
69ee7e02
File moved
frontends/read_
ilang/read_ilang
.ys
→
frontends/read_
rtlil/read_rtlil
.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
...
...
frontends/read_
ilang/read_ilang
_fsm.ys
→
frontends/read_
rtlil/read_rtlil
_fsm.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
...
...
frontends/read_
ilang/read_ilang
_lib.ys
→
frontends/read_
rtlil/read_rtlil
_lib.ys
View file @
69ee7e02
...
...
@@ -2,7 +2,7 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -lib ilang.ilang
read_
rtlil -lib rtlil.il
dump -n -o file1.il
frontends/read_
ilang/read_ilang
_lib_fsm.ys
→
frontends/read_
rtlil/read_rtlil
_lib_fsm.ys
View file @
69ee7e02
...
...
@@ -2,7 +2,7 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -lib ilang.ilang
read_
rtlil -lib rtlil.il
dump -n -o file1.il
frontends/read_
ilang/read_ilang
_lib_tri.ys
→
frontends/read_
rtlil/read_rtlil
_lib_tri.ys
View file @
69ee7e02
...
...
@@ -2,8 +2,8 @@ read_verilog ../top_tri.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -lib ilang.ilang
read_
ilang ilang.ilang
read_
rtlil -lib rtlil.il
read_
rtlil rtlil.il
dump -n -o file1.il
frontends/read_
ilang/read_ilang
_mem.ys
→
frontends/read_
rtlil/read_rtlil
_mem.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_mem.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 2 t:$dff
...
...
frontends/read_
ilang/read_ilang
_mux.ys
→
frontends/read_
rtlil/read_rtlil
_mux.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_mux.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$shiftx
...
...
frontends/read_
ilang/read_ilang
_nooverwrite.ys
→
frontends/read_
rtlil/read_rtlil
_nooverwrite.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -nooverwrite ilang.ilang
read_
rtlil -nooverwrite rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
...
...
frontends/read_
ilang/read_ilang
_nooverwrite_fsm.ys
→
frontends/read_
rtlil/read_rtlil
_nooverwrite_fsm.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -nooverwrite ilang.ilang
read_
rtlil -nooverwrite rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
...
...
frontends/read_
ilang/read_ilang
_overwrite.ys
→
frontends/read_
rtlil/read_rtlil
_overwrite.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -overwrite ilang.ilang
read_
rtlil -overwrite rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
...
...
frontends/read_
ilang/read_ilang
_overwrite_fsm.ys
→
frontends/read_
rtlil/read_rtlil
_overwrite_fsm.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang -overwrite ilang.ilang
read_
rtlil -overwrite rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
...
...
frontends/read_
ilang/read_ilang
_parse_error.ys
→
frontends/read_
rtlil/read_rtlil
_parse_error.ys
View file @
69ee7e02
logger -expect error "Parser error in line 110" 1
read_
ilang ../ilang.ilang
read_
rtlil ../error.il
frontends/read_
ilang/read_ilang
_selected.ys
→
frontends/read_
rtlil/read_rtlil
_selected.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_
ilang -selected ilang.ilang
write_
rtlil -selected rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
...
...
frontends/read_
ilang/read_ilang
_selected_fsm.ys
→
frontends/read_
rtlil/read_rtlil
_selected_fsm.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_
ilang -selected ilang.ilang
write_
rtlil -selected rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
...
...
frontends/read_
ilang/read_ilang
_tri.ys
→
frontends/read_
rtlil/read_rtlil
_tri.ys
View file @
69ee7e02
...
...
@@ -2,9 +2,9 @@ read_verilog ../top_tri.v
proc
memory
dump -o file.il
write_
ilang ilang.ilang
write_
rtlil rtlil.il
design -reset
read_
ilang ilang.ilang
read_
rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 2 t:$mux
frontends/read_
ilang
/top.v
→
frontends/read_
rtlil
/top.v
View file @
69ee7e02
File moved
frontends/read_
ilang
/top_fsm.v
→
frontends/read_
rtlil
/top_fsm.v
View file @
69ee7e02
File moved
frontends/read_
ilang
/top_mem.v
→
frontends/read_
rtlil
/top_mem.v
View file @
69ee7e02
File moved
frontends/read_
ilang
/top_mux.v
→
frontends/read_
rtlil
/top_mux.v
View file @
69ee7e02
File moved
frontends/read_
ilang
/top_tri.v
→
frontends/read_
rtlil
/top_tri.v
View file @
69ee7e02
File moved
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