Commit 69ee7e02 by Miodrag Milanovic

Rename ilang to rtlil

parent 627a3d12
......@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
......
......@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
......
......@@ -2,7 +2,7 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -lib ilang.ilang
read_rtlil -lib rtlil.il
dump -n -o file1.il
......@@ -2,7 +2,7 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -lib ilang.ilang
read_rtlil -lib rtlil.il
dump -n -o file1.il
......@@ -2,8 +2,8 @@ read_verilog ../top_tri.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -lib ilang.ilang
read_ilang ilang.ilang
read_rtlil -lib rtlil.il
read_rtlil rtlil.il
dump -n -o file1.il
......@@ -2,9 +2,9 @@ read_verilog ../top_mem.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 2 t:$dff
......
......@@ -2,9 +2,9 @@ read_verilog ../top_mux.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$shiftx
......
......@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -nooverwrite ilang.ilang
read_rtlil -nooverwrite rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
......
......@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -nooverwrite ilang.ilang
read_rtlil -nooverwrite rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
......
......@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -overwrite ilang.ilang
read_rtlil -overwrite rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
......
......@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang -overwrite ilang.ilang
read_rtlil -overwrite rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
......
logger -expect error "Parser error in line 110" 1
read_ilang ../ilang.ilang
read_rtlil ../error.il
......@@ -2,9 +2,9 @@ read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang -selected ilang.ilang
write_rtlil -selected rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
select -assert-count 1 t:$and
......
......@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang -selected ilang.ilang
write_rtlil -selected rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 1 t:$add
......
......@@ -2,9 +2,9 @@ read_verilog ../top_tri.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
write_rtlil rtlil.il
design -reset
read_ilang ilang.ilang
read_rtlil rtlil.il
dump -n -o file1.il
stat
select -assert-count 2 t:$mux
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